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Tue, 27 May 2025 00:33:43 -0700 (PDT) Received: from [172.16.25.47] ([195.53.115.74]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4d47c0684sm6706179f8f.44.2025.05.27.00.33.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 May 2025 00:33:43 -0700 (PDT) Message-ID: Date: Tue, 27 May 2025 08:33:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/12] target/arm: Fill in TCGCPUOps.pointer_wrap To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: foss@percivaleng.com, qemu-arm@nongnu.org, Gustavo Romero References: <20250504205714.3432096-1-richard.henderson@linaro.org> <20250504205714.3432096-5-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/26/25 19:21, Philippe Mathieu-Daudé wrote: > +Gustavo > > On 4/5/25 22:57, Richard Henderson wrote: >> For a-profile, check A32 vs A64 state. >> For m-profile, use cpu_pointer_wrap_uint32. >> >> Cc: qemu-arm@nongnu.org >> Signed-off-by: Richard Henderson >> --- >>   target/arm/cpu.c         | 24 ++++++++++++++++++++++++ >>   target/arm/tcg/cpu-v7m.c |  1 + >>   2 files changed, 25 insertions(+) >> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 45cb6fd7ee..18edcf49c6 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -2710,6 +2710,29 @@ static const struct SysemuCPUOps arm_sysemu_ops = { >>   #endif >>   #ifdef CONFIG_TCG >> +#ifndef CONFIG_USER_ONLY >> +static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx, >> +                                   vaddr result, vaddr base) >> +{ >> +    /* >> +     * The Stage2 and Phys indexes are only used for ptw on arm32, >> +     * and all pte's are aligned, so we never produce a wrap for these. >> +     * Double check that we're not truncating a 40-bit physical address. >> +     */ >> +    assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK)); >> + >> +    if (!is_a64(cpu_env(cs))) { >> +        return (uint32_t)result; >> +    } >> + >> +    /* >> +     * TODO: For FEAT_CPA2, decide how to we want to resolve >> +     * Unpredictable_CPACHECK in AddressIncrement. >> +     */ >> +    return result; >> +} >> +#endif /* !CONFIG_USER_ONLY */ >> + >>   static const TCGCPUOps arm_tcg_ops = { >>       .mttcg_supported = true, >>       /* ARM processors have a weak memory model */ >> @@ -2729,6 +2752,7 @@ static const TCGCPUOps arm_tcg_ops = { >>       .untagged_addr = aarch64_untagged_addr, >>   #else >>       .tlb_fill_align = arm_cpu_tlb_fill_align, >> +    .pointer_wrap = aprofile_pointer_wrap, > > IIUC this is also used by non A-profiles (R-profiles and > non Cortex cores). Yes, r-profile is mostly a-profile. Those non-cortex cores are also a-profile: armv[456]. The point is the separation between m-profile and not. In particular, the mmu indexes are different between A and M (see ARM_MMU_IDX_TYPE_MASK). The assert would not be valid for m-profile. We can avoid a check vs ARM_FEATURE_M by only using this function for not-m-profile. r~