Re: [Qemu-devel] sh4: further updates

["Magnus Damm" <magnus.damm@gmail.com>]

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Hi Thiemo!

Thanks for testing and applying!

On 5/14/07, Thiemo Seufer <ths@networkno.de> wrote:
> The sh4-fpu-new patch fails to build (on ppc/Linux) with:
>
> gcc-3.4 -Wall -O2 -g -fno-strict-aliasing -I. -I.. -I/home/ths/qemu/qemu-write/target-sh4 -I/home/ths/qemu/qemu-write -D__powerpc__ -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -I/home/ths/qemu/qemu-write/fpu -I/home/ths/qemu/qemu-write/slirp    -c -o translate-op.o /home/ths/qemu/qemu-write/translate-op.c
> In file included from /home/ths/qemu/qemu-write/translate-op.c:36:
> ./op.h: In function `dyngen_code':
> ./op.h:1220: error: syntax error before ')' token
> ./op.h:1221: error: syntax error before ')' token
> make[1]: *** [translate-op.o] Error 1
> make[1]: Leaving directory `/home/ths/qemu/qemu-write/sh4-softmmu'
> make: *** [subdir-sh4-softmmu] Error 2

Does the attached patch fix your problem? Apply on top of sh4-fpu-new.

/ magnus

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sh4: Fix new fpu opcodes

This patch works around problems with references to the cst8 section that
occured on powerpc. This fix has been tested using gentoo crossdev and a
combination of gcc-3.4.6 and glibc-2.4.

Signed-off-by: Magnus Damm <damm@igel.co.jp>

--- 0002/target-sh4/op.c
+++ work/target-sh4/op.c	2007-05-14 17:46:06.000000000 +0900
@@ -804,9 +804,9 @@ void OPPROTO op_ftrc_DT(void)
     RETURN();
 }
 
-void OPPROTO op_movl_T0_FT0(void)
+void OPPROTO op_fmov_T0_frN(void)
 {
-    FT0 = T0;
+    *(unsigned int *)&env->fregs[PARAM1] = T0;
     RETURN();
 }
 
--- 0002/target-sh4/translate.c
+++ work/target-sh4/translate.c	2007-05-14 17:46:20.000000000 +0900
@@ -1156,16 +1156,14 @@ void decode_opc(DisasContext * ctx)
     case 0xf08d:		/* fldi0 FRn */
 	if (!(ctx->fpscr & FPSCR_PR)) {
 	    gen_op_movl_imm_T0(0);
-	    gen_op_movl_T0_FT0();
-	    gen_op_fmov_FT0_frN(FREG(B11_8));
+	    gen_op_fmov_T0_frN(FREG(B11_8));
 	    return;
 	}
 	break;
     case 0xf09d:		/* fldi1 FRn */
 	if (!(ctx->fpscr & FPSCR_PR)) {
 	    gen_op_movl_imm_T0(0x3f800000);
-	    gen_op_movl_T0_FT0();
-	    gen_op_fmov_FT0_frN(FREG(B11_8));
+	    gen_op_fmov_T0_frN(FREG(B11_8));
 	    return;
 	}
 	break;