From: "Magnus Damm" <magnus.damm@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] sh4: more patches
Date: Fri, 22 Jun 2007 16:44:57 +0900 [thread overview]
Message-ID: <aec7e5c30706220044u5b4ae7felc64ed595454ebb37@mail.gmail.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]
Hi everyone,
Here comes a few more patches for the sh4 emulator. The should be
applied on top of the patches that I posted a few weeks ago:
http://www.mail-archive.com/qemu-devel@nongnu.org/msg10830.html
Good news is that the user space emulator is in a much better shape
now - with all the patches applied I'm successfully running a static
busybox binary compiled for sh4 using qemu-sh4.
The method used to locate emulation bugs may be of value for other
fellow qemu hackers. I've written a small gdb script that single steps
in an endless loop dumping registers between each instruction. Then
I've used this script on both real target hardware (using gdbserver)
and using the gdbstub provided by qemu. Finally the traces have been
compared. I have more patches for this if anyone is interested...
The patches attached in this email contain the following fixes:
- sh4: Emulate more fpu opcodes
- sh4: Swap word order when accessing double floats
- sh4: Document FPSCR usage
- sh4: Ignore PR flag in FPSCR when performing fmov
- sh4: Use DREG() instead of XREG() wherever possible
Could someone please comment or commit? =)
Thank you!
/ magnus
[-- Attachment #2: qemu-cvs_20070611-sh4-fpu-ops.patch --]
[-- Type: application/octet-stream, Size: 6622 bytes --]
sh4: Emulate more fpu opcodes
This patch adds more fpu opcodes to the sh4 emulator. Exceptions are not
supported yet though and flag emulation needs further work.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
cpu.h | 1
op.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
translate.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 183 insertions(+), 1 deletion(-)
--- 0002/target-sh4/cpu.h
+++ work/target-sh4/cpu.h 2007-06-11 12:37:41.000000000 +0900
@@ -99,6 +99,7 @@ typedef struct CPUSH4State {
/* temporary float registers */
float32 ft0, ft1;
float64 dt0, dt1;
+ float_status fp_status;
/* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */
--- 0001/target-sh4/op.c
+++ work/target-sh4/op.c 2007-06-11 12:40:13.000000000 +0900
@@ -509,6 +509,9 @@ void OPPROTO op_##store##_##target##_T0
void OPPROTO op_lds_T0_fpscr(void)
{
env->fpscr = T0 & 0x003fffff;
+ env->fp_status.float_rounding_mode = T0 & 0x01 ?
+ float_round_to_zero : float_round_nearest_even;
+
RETURN();
}
@@ -705,6 +708,18 @@ void OPPROTO op_fmov_drN_DT0(void)
RETURN();
}
+void OPPROTO op_fmov_frN_FT1(void)
+{
+ FT1 = *(float32 *)&env->fregs[PARAM1];
+ RETURN();
+}
+
+void OPPROTO op_fmov_drN_DT1(void)
+{
+ DT1 = *(float64 *)&env->fregs[PARAM1];
+ RETURN();
+}
+
void OPPROTO op_fmov_FT0_frN(void)
{
*(float32 *)&env->fregs[PARAM1] = FT0;
@@ -717,6 +732,84 @@ void OPPROTO op_fmov_DT0_drN(void)
RETURN();
}
+void OPPROTO op_fadd_FT(void)
+{
+ FT0 = float32_add(FT0, FT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fadd_DT(void)
+{
+ DT0 = float64_add(DT0, DT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fsub_FT(void)
+{
+ FT0 = float32_sub(FT0, FT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fsub_DT(void)
+{
+ DT0 = float64_sub(DT0, DT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fmul_FT(void)
+{
+ FT0 = float32_mul(FT0, FT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fmul_DT(void)
+{
+ DT0 = float64_mul(DT0, DT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fdiv_FT(void)
+{
+ FT0 = float32_div(FT0, FT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fdiv_DT(void)
+{
+ DT0 = float64_div(DT0, DT1, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_float_FT(void)
+{
+ FT0 = int32_to_float32(env->fpul, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_float_DT(void)
+{
+ DT0 = int32_to_float64(env->fpul, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_ftrc_FT(void)
+{
+ env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_ftrc_DT(void)
+{
+ env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status);
+ RETURN();
+}
+
+void OPPROTO op_fmov_T0_frN(void)
+{
+ *(unsigned int *)&env->fregs[PARAM1] = T0;
+ RETURN();
+}
+
void OPPROTO op_dec1_rN(void)
{
env->gregs[PARAM1] -= 1;
--- 0003/target-sh4/translate.c
+++ work/target-sh4/translate.c 2007-06-11 12:37:45.000000000 +0900
@@ -131,7 +131,13 @@ void cpu_sh4_reset(CPUSH4State * env)
#endif
env->vbr = 0;
env->pc = 0xA0000000;
- env->fpscr = 0x00040001;
+#if defined(CONFIG_USER_ONLY)
+ env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
+ env->fp_status.float_rounding_mode = float_round_nearest_even; /* ?! */
+#else
+ env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
+ env->fp_status.float_rounding_mode = float_round_to_zero;
+#endif
env->mmucr = 0;
}
@@ -238,6 +244,7 @@ static void gen_delayed_conditional_jump
#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
+#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
#define CHECK_NOT_DELAY_SLOT \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
@@ -768,6 +775,49 @@ void decode_opc(DisasContext * ctx)
gen_op_stfl_FT0_T1(ctx);
}
return;
+ case 0xf000: /* fadd Rm,Rn */
+ case 0xf001: /* fsub Rm,Rn */
+ case 0xf002: /* fmul Rm,Rn */
+ case 0xf003: /* fdiv Rm,Rn */
+ case 0xf004: /* fcmp/eq Rm,Rn */
+ case 0xf005: /* fcmp/gt Rm,Rn */
+ if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->opcode & 0x0110)
+ break; /* illegal instruction */
+ gen_op_fmov_drN_DT1(DREG(B7_4));
+ gen_op_fmov_drN_DT0(DREG(B11_8));
+ }
+ else {
+ gen_op_fmov_frN_FT1(FREG(B7_4));
+ gen_op_fmov_frN_FT0(FREG(B11_8));
+ }
+
+ switch (ctx->opcode & 0xf00f) {
+ case 0xf000: /* fadd Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT();
+ break;
+ case 0xf001: /* fsub Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT();
+ break;
+ case 0xf002: /* fmul Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT();
+ break;
+ case 0xf003: /* fdiv Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT();
+ break;
+ case 0xf004: /* fcmp/eq Rm,Rn */
+ return;
+ case 0xf005: /* fcmp/gt Rm,Rn */
+ return;
+ }
+
+ if (ctx->fpscr & FPSCR_PR) {
+ gen_op_fmov_DT0_drN(DREG(B11_8));
+ }
+ else {
+ gen_op_fmov_FT0_frN(FREG(B11_8));
+ }
+ return;
}
switch (ctx->opcode & 0xff00) {
@@ -1079,6 +1129,44 @@ void decode_opc(DisasContext * ctx)
gen_op_fmov_frN_FT0(FREG(B11_8));
gen_op_movl_FT0_fpul();
return;
+ case 0xf02d: /* float FPUL,FRn/DRn */
+ if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->opcode & 0x0100)
+ break; /* illegal instruction */
+ gen_op_float_DT();
+ gen_op_fmov_DT0_drN(DREG(B11_8));
+ }
+ else {
+ gen_op_float_FT();
+ gen_op_fmov_FT0_frN(FREG(B11_8));
+ }
+ return;
+ case 0xf03d: /* ftrc FRm/DRm,FPUL */
+ if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->opcode & 0x0100)
+ break; /* illegal instruction */
+ gen_op_fmov_drN_DT0(DREG(B11_8));
+ gen_op_ftrc_DT();
+ }
+ else {
+ gen_op_fmov_frN_FT0(FREG(B11_8));
+ gen_op_ftrc_FT();
+ }
+ return;
+ case 0xf08d: /* fldi0 FRn */
+ if (!(ctx->fpscr & FPSCR_PR)) {
+ gen_op_movl_imm_T0(0);
+ gen_op_fmov_T0_frN(FREG(B11_8));
+ return;
+ }
+ break;
+ case 0xf09d: /* fldi1 FRn */
+ if (!(ctx->fpscr & FPSCR_PR)) {
+ gen_op_movl_imm_T0(0x3f800000);
+ gen_op_fmov_T0_frN(FREG(B11_8));
+ return;
+ }
+ break;
}
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
[-- Attachment #3: qemu-cvs_20070611-sh4-fpu-word-order.patch --]
[-- Type: application/octet-stream, Size: 1472 bytes --]
sh4: Swap word order when accessing double floats
This patch makes sure that double floats get their word order correct when
accessing the FPU register pair as a double.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
cpu-all.h | 12 ++++++++++++
target-sh4/op.c | 6 +++---
2 files changed, 15 insertions(+), 3 deletions(-)
--- 0001/cpu-all.h
+++ work/cpu-all.h 2007-06-11 12:42:32.000000000 +0900
@@ -135,6 +135,18 @@ typedef union {
uint64_t ll;
} CPU_DoubleU;
+static inline float64 word_swap(float64 d)
+{
+ CPU_DoubleU u;
+ uint32_t i;
+
+ u.d = d;
+ i = u.l.lower;
+ u.l.lower = u.l.upper;
+ u.l.upper = i;
+ return u.d;
+}
+
/* CPU memory access without any memory or io remapping */
/*
--- 0004/target-sh4/op.c
+++ work/target-sh4/op.c 2007-06-11 12:42:32.000000000 +0900
@@ -704,7 +704,7 @@ void OPPROTO op_fmov_frN_FT0(void)
void OPPROTO op_fmov_drN_DT0(void)
{
- DT0 = *(float64 *)&env->fregs[PARAM1];
+ DT0 = word_swap(ldfq_le_p(&env->fregs[PARAM1]));
RETURN();
}
@@ -716,7 +716,7 @@ void OPPROTO op_fmov_frN_FT1(void)
void OPPROTO op_fmov_drN_DT1(void)
{
- DT1 = *(float64 *)&env->fregs[PARAM1];
+ DT1 = word_swap(ldfq_le_p(&env->fregs[PARAM1]));
RETURN();
}
@@ -728,7 +728,7 @@ void OPPROTO op_fmov_FT0_frN(void)
void OPPROTO op_fmov_DT0_drN(void)
{
- *(float64 *)&env->fregs[PARAM1] = DT0;
+ stfq_le_p(&env->fregs[PARAM1], word_swap(DT0));
RETURN();
}
[-- Attachment #4: qemu-cvs_20070507-sh4-fpu-fpscr-comments.patch --]
[-- Type: application/octet-stream, Size: 5180 bytes --]
sh4: Document FPSCR usage
This patch extends per opcode comments to include FPSCR usage. These comments
are useful when implementing proper fpu exception handling in the future. This
patch contains no logic changes.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
translate.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
--- 0003/target-sh4/translate.c
+++ work/target-sh4/translate.c 2007-05-07 17:29:32.000000000 +0900
@@ -642,7 +642,7 @@ void decode_opc(DisasContext * ctx)
gen_op_movl_rN_T0(REG(B7_4));
gen_op_xor_T0_rN(REG(B11_8));
return;
- case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn */
+ case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_fmov_DT0_drN(XREG(B11_8));
@@ -656,7 +656,7 @@ void decode_opc(DisasContext * ctx)
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
- case 0xf00a: /* fmov {F,D,X}Rm,@Rn */
+ case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
@@ -673,7 +673,7 @@ void decode_opc(DisasContext * ctx)
gen_op_stfl_FT0_T1(ctx);
}
return;
- case 0xf008: /* fmov @Rm,{F,D,X}Rn */
+ case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
@@ -690,7 +690,7 @@ void decode_opc(DisasContext * ctx)
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
- case 0xf009: /* fmov @Rm+,{F,D,X}Rn */
+ case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
@@ -710,7 +710,7 @@ void decode_opc(DisasContext * ctx)
gen_op_inc4_rN(REG(B7_4));
}
return;
- case 0xf00b: /* fmov {F,D,X}Rm,@-Rn */
+ case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_dec8_rN(REG(B11_8));
gen_op_fmov_drN_DT0(XREG(B7_4));
@@ -730,7 +730,7 @@ void decode_opc(DisasContext * ctx)
gen_op_stfl_FT0_T1(ctx);
}
return;
- case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm */
+ case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
@@ -750,7 +750,7 @@ void decode_opc(DisasContext * ctx)
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
- case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) */
+ case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_PR) {
gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
@@ -770,12 +770,12 @@ void decode_opc(DisasContext * ctx)
gen_op_stfl_FT0_T1(ctx);
}
return;
- case 0xf000: /* fadd Rm,Rn */
- case 0xf001: /* fsub Rm,Rn */
- case 0xf002: /* fmul Rm,Rn */
- case 0xf003: /* fdiv Rm,Rn */
- case 0xf004: /* fcmp/eq Rm,Rn */
- case 0xf005: /* fcmp/gt Rm,Rn */
+ case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
+ case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
+ case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
+ case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
+ case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
+ case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0110)
break; /* illegal instruction */
@@ -1116,15 +1116,15 @@ void decode_opc(DisasContext * ctx)
case 0x401b: /* tas.b @Rn */
gen_op_tasb_rN(REG(B11_8));
return;
- case 0xf00d: /* fsts FPUL,FRn */
+ case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
gen_op_movl_fpul_FT0();
gen_op_fmov_FT0_frN(FREG(B11_8));
return;
- case 0xf01d: /* flds FRm.FPUL */
+ case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
gen_op_fmov_frN_FT0(FREG(B11_8));
gen_op_movl_FT0_fpul();
return;
- case 0xf02d: /* float FPUL,FRn/DRn */
+ case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
@@ -1136,7 +1136,7 @@ void decode_opc(DisasContext * ctx)
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
- case 0xf03d: /* ftrc FRm/DRm,FPUL */
+ case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
@@ -1148,7 +1148,7 @@ void decode_opc(DisasContext * ctx)
gen_op_ftrc_FT();
}
return;
- case 0xf08d: /* fldi0 FRn */
+ case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
if (!(ctx->fpscr & FPSCR_PR)) {
gen_op_movl_imm_T0(0);
gen_op_movl_T0_FT0();
@@ -1156,7 +1156,7 @@ void decode_opc(DisasContext * ctx)
return;
}
break;
- case 0xf09d: /* fldi1 FRn */
+ case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
if (!(ctx->fpscr & FPSCR_PR)) {
gen_op_movl_imm_T0(0x3f800000);
gen_op_movl_T0_FT0();
[-- Attachment #5: qemu-cvs_20070622-sh4-fpu-fmov-ignore-fpscr-pr.patch --]
[-- Type: application/octet-stream, Size: 3694 bytes --]
sh4: Ignore PR flag in FPSCR when performing fmov
This patch makes sure qemu behaves like a real 7751 target and ignores the PR
flag in FPSCR when performing fmov operations.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
translate.c | 45 +++++++--------------------------------------
1 file changed, 7 insertions(+), 38 deletions(-)
--- 0009/target-sh4/translate.c
+++ work/target-sh4/translate.c 2007-06-22 16:12:51.000000000 +0900
@@ -648,10 +648,7 @@ void decode_opc(DisasContext * ctx)
gen_op_xor_T0_rN(REG(B11_8));
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_fmov_drN_DT0(XREG(B7_4));
- gen_op_fmov_DT0_drN(XREG(B11_8));
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0110)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(XREG(B7_4));
@@ -662,11 +659,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_fmov_drN_DT0(XREG(B7_4));
- gen_op_movl_rN_T1(REG(B11_8));
- gen_op_stfq_DT0_T1(ctx);
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(XREG(B7_4));
@@ -679,11 +672,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_movl_rN_T0(REG(B7_4));
- gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
@@ -696,12 +685,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_movl_rN_T0(REG(B7_4));
- gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
- gen_op_inc8_rN(REG(B7_4));
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
@@ -716,12 +700,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_dec8_rN(REG(B11_8));
- gen_op_fmov_drN_DT0(XREG(B7_4));
- gen_op_movl_rN_T1(REG(B11_8));
- gen_op_stfq_DT0_T1(ctx);
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_dec8_rN(REG(B11_8));
@@ -736,12 +715,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_movl_rN_T0(REG(B7_4));
- gen_op_add_rN_T0(REG(0));
- gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
@@ -756,12 +730,7 @@ void decode_opc(DisasContext * ctx)
}
return;
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
- if (ctx->fpscr & FPSCR_PR) {
- gen_op_fmov_drN_DT0(XREG(B7_4));
- gen_op_movl_rN_T1(REG(B11_8));
- gen_op_add_rN_T1(REG(0));
- gen_op_stfq_DT0_T1(ctx);
- } else if (ctx->fpscr & FPSCR_SZ) {
+ if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(XREG(B7_4));
[-- Attachment #6: qemu-cvs_20070508-sh4-dreg-fixes.patch --]
[-- Type: application/octet-stream, Size: 2702 bytes --]
sh4: Use DREG() instead of XREG() wherever possible
Replace XREG() with DREG() if the lowest register bits are known to be zero.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- 0006/target-sh4/translate.c
+++ work/target-sh4/translate.c 2007-05-08 13:19:40.000000000 +0900
@@ -649,8 +649,8 @@ void decode_opc(DisasContext * ctx)
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0110)
break; /* illegal instruction */
- gen_op_fmov_drN_DT0(XREG(B7_4));
- gen_op_fmov_DT0_drN(XREG(B11_8));
+ gen_op_fmov_drN_DT0(DREG(B7_4));
+ gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_fmov_FT0_frN(FREG(B11_8));
@@ -664,7 +664,7 @@ void decode_opc(DisasContext * ctx)
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
- gen_op_fmov_drN_DT0(XREG(B7_4));
+ gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
@@ -683,7 +683,7 @@ void decode_opc(DisasContext * ctx)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
+ gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfl_T0_FT0(ctx);
@@ -701,7 +701,7 @@ void decode_opc(DisasContext * ctx)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
+ gen_op_fmov_DT0_drN(DREG(B11_8));
gen_op_inc8_rN(REG(B7_4));
} else {
gen_op_movl_rN_T0(REG(B7_4));
@@ -720,7 +720,7 @@ void decode_opc(DisasContext * ctx)
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_dec8_rN(REG(B11_8));
- gen_op_fmov_drN_DT0(XREG(B7_4));
+ gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
@@ -742,7 +742,7 @@ void decode_opc(DisasContext * ctx)
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(XREG(B11_8));
+ gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
@@ -759,7 +759,7 @@ void decode_opc(DisasContext * ctx)
} else if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
- gen_op_fmov_drN_DT0(XREG(B7_4));
+ gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stfq_DT0_T1(ctx);
next reply other threads:[~2007-06-22 7:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-22 7:44 Magnus Damm [this message]
2007-06-22 11:48 ` [Qemu-devel] sh4: more patches Thiemo Seufer
2007-06-25 6:42 ` Magnus Damm
2007-06-25 12:01 ` Thiemo Seufer
2007-07-04 4:19 ` Magnus Damm
2007-07-25 1:02 ` Paul Mundt
2007-06-25 15:28 ` Blue Swirl
2007-07-04 4:44 ` Magnus Damm
2007-07-04 18:01 ` Blue Swirl
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