From: "Magnus Damm" <magnus.damm@gmail.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] sh4: more patches
Date: Mon, 25 Jun 2007 15:42:02 +0900 [thread overview]
Message-ID: <aec7e5c30706242342s6f31937ft5900980ab2e21edd@mail.gmail.com> (raw)
In-Reply-To: <20070622114819.GD25967@networkno.de>
[-- Attachment #1: Type: text/plain, Size: 475 bytes --]
Hi Thiemo,
Thanks for the review and commit help!
On 6/22/07, Thiemo Seufer <ths@networkno.de> wrote:
> Magnus Damm wrote:
> > The patches attached in this email contain the following fixes:
> >
> > - sh4: Swap word order when accessing double floats
>
> Doesn't this one also depend on the host endianness?
Yeah, correct. Thanks for pointing that out. The attached patch should
solve things in a better and more host endian neutral way. Please
commit.
Thanks!
/ magnus
[-- Attachment #2: qemu-cvs_20070625-sh4-fpu-double-word-order.patch --]
[-- Type: application/octet-stream, Size: 2127 bytes --]
sh4: Fix word order when accessing double floats
This patch makes sure that double floats get their word order correct when
accessing the FPU register pair as a double.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
cpu.h | 2 +-
op.c | 24 ++++++++++++++++++------
2 files changed, 19 insertions(+), 7 deletions(-)
--- 0001/target-sh4/cpu.h
+++ work/target-sh4/cpu.h 2007-06-25 14:43:47.000000000 +0900
@@ -80,7 +80,7 @@ typedef struct tlb_t {
typedef struct CPUSH4State {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
- uint32_t fregs[32]; /* floating point registers */
+ float32 fregs[32]; /* floating point registers */
uint32_t sr; /* status register */
uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */
--- 0001/target-sh4/op.c
+++ work/target-sh4/op.c 2007-06-25 15:28:12.000000000 +0900
@@ -698,37 +698,49 @@ void OPPROTO op_movl_imm_rN(void)
void OPPROTO op_fmov_frN_FT0(void)
{
- FT0 = *(float32 *)&env->fregs[PARAM1];
+ FT0 = env->fregs[PARAM1];
RETURN();
}
void OPPROTO op_fmov_drN_DT0(void)
{
- DT0 = *(float64 *)&env->fregs[PARAM1];
+ CPU_DoubleU d;
+
+ d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
+ d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
+ DT0 = d.d;
RETURN();
}
void OPPROTO op_fmov_frN_FT1(void)
{
- FT1 = *(float32 *)&env->fregs[PARAM1];
+ FT1 = env->fregs[PARAM1];
RETURN();
}
void OPPROTO op_fmov_drN_DT1(void)
{
- DT1 = *(float64 *)&env->fregs[PARAM1];
+ CPU_DoubleU d;
+
+ d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
+ d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
+ DT1 = d.d;
RETURN();
}
void OPPROTO op_fmov_FT0_frN(void)
{
- *(float32 *)&env->fregs[PARAM1] = FT0;
+ env->fregs[PARAM1] = FT0;
RETURN();
}
void OPPROTO op_fmov_DT0_drN(void)
{
- *(float64 *)&env->fregs[PARAM1] = DT0;
+ CPU_DoubleU d;
+
+ d.d = DT0;
+ *(uint32_t *)&env->fregs[PARAM1] = d.l.upper;
+ *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
RETURN();
}
next prev parent reply other threads:[~2007-06-25 6:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-22 7:44 [Qemu-devel] sh4: more patches Magnus Damm
2007-06-22 11:48 ` Thiemo Seufer
2007-06-25 6:42 ` Magnus Damm [this message]
2007-06-25 12:01 ` Thiemo Seufer
2007-07-04 4:19 ` Magnus Damm
2007-07-25 1:02 ` Paul Mundt
2007-06-25 15:28 ` Blue Swirl
2007-07-04 4:44 ` Magnus Damm
2007-07-04 18:01 ` Blue Swirl
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