From: "Magnus Damm" <magnus.damm@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] sh4: more system emulator patches
Date: Wed, 14 Nov 2007 20:14:20 +0900 [thread overview]
Message-ID: <aec7e5c30711140314j7b10fb4dw30259d0454d91888@mail.gmail.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 608 bytes --]
Hi everyone,
Here comes another batch of sh4 system emulator patches.
sh: add sh.h header
sh_serial: enable tx after reset
sh_intc: improve interrupt controller code
sh: connect cpu core to interrupt controller
sh_timer: add interrupt support
These patches mainly improve the sh interrupt controller code.
Interrupt delivery is however disabled by default since the sh4 cpu
core code still has some outstanding interrupt issues. People
interested in hacking and testing can enable interrupt delivery by
commenting out INTC_IRQS_DISABLED in hw/sh_intc.c.
Please apply in attached order. Thanks!
/ magnus
[-- Attachment #2: qemu-cvs-20071109-sh-header.patch --]
[-- Type: application/octet-stream, Size: 1710 bytes --]
sh: add sh.h header
This patch adds the header file sh.h
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
hw/sh.h | 11 +++++++++++
hw/sh7750.c | 1 +
hw/sh_serial.c | 1 +
hw/sh_timer.c | 1 +
vl.h | 5 -----
5 files changed, 14 insertions(+), 5 deletions(-)
--- /dev/null
+++ work/hw/sh.h 2007-11-09 19:03:12.000000000 +0900
@@ -0,0 +1,11 @@
+#ifndef __SH_H__
+#define __SH_H__
+
+#include "sh_intc.h"
+
+/* sh_serial.c */
+#define SH_SERIAL_FEAT_SCIF (1 << 0)
+void sh_serial_init (target_phys_addr_t base, int feat,
+ uint32_t freq, CharDriverState *chr);
+
+#endif /* __SH_H__ */
--- 0001/hw/sh7750.c
+++ work/hw/sh7750.c 2007-11-09 19:09:33.000000000 +0900
@@ -27,6 +27,7 @@
#include "vl.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
+#include "sh.h"
#include "sh_intc.h"
#define NB_DEVICES 4
--- 0002/hw/sh_serial.c
+++ work/hw/sh_serial.c 2007-11-09 19:06:11.000000000 +0900
@@ -25,6 +25,7 @@
* THE SOFTWARE.
*/
#include "vl.h"
+#include "sh.h"
#include <assert.h>
//#define DEBUG_SERIAL
--- 0001/hw/sh_timer.c
+++ work/hw/sh_timer.c 2007-11-09 19:06:17.000000000 +0900
@@ -9,6 +9,7 @@
*/
#include "vl.h"
+#include "sh.h"
//#define DEBUG_TIMER
--- 0001/vl.h
+++ work/vl.h 2007-11-09 19:06:55.000000000 +0900
@@ -1557,11 +1557,6 @@ int sh7750_register_io_device(struct SH7
#define TMU012_FEAT_EXTCLK (1 << 2)
void tmu012_init(uint32_t base, int feat, uint32_t freq);
-/* sh_serial.c */
-#define SH_SERIAL_FEAT_SCIF (1 << 0)
-void sh_serial_init (target_phys_addr_t base, int feat,
- uint32_t freq, CharDriverState *chr);
-
/* tc58128.c */
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
[-- Attachment #3: qemu-cvs-20071109-sh-serial-tx-enabled-by-default.patch --]
[-- Type: application/octet-stream, Size: 595 bytes --]
sh_serial: enable tx after reset
This patch enables tx directly after reset so linux kernel early printk works
without boot loader.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
hw/sh_serial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- 0001/hw/sh_serial.c
+++ work/hw/sh_serial.c 2007-11-09 17:46:07.000000000 +0900
@@ -291,7 +291,7 @@ void sh_serial_init (target_phys_addr_t
s->smr = 0;
s->brr = 0xff;
- s->scr = 0;
+ s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
s->sptr = 0;
if (feat & SH_SERIAL_FEAT_SCIF) {
[-- Attachment #4: qemu-cvs-20071109b-sh-intc-update.patch --]
[-- Type: application/octet-stream, Size: 7159 bytes --]
sh_intc: improve interrupt controller code
This patch improves the sh interrupt controller code. All interrupt sources
provided by cpu-specific intc tables are now fully emulated. Interrupts are
however still not delivered since the cpu core needs more work. Brave users
can comment out INTC_IRQS_DISABLED to enable interrupt delivery.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
hw/sh_intc.c | 124 +++++++++++++++++++++++++++++++++++++++++++++-------------
hw/sh_intc.h | 8 +++
2 files changed, 104 insertions(+), 28 deletions(-)
--- 0001/hw/sh_intc.c
+++ work/hw/sh_intc.c 2007-11-09 20:19:00.000000000 +0900
@@ -13,10 +13,92 @@
#include "vl.h"
//#define DEBUG_INTC
+//#define DEBUG_INTC_SOURCES
+#define INTC_IRQS_DISABLED
#define INTC_A7(x) ((x) & 0x1fffffff)
#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))
+void sh_intc_toggle_source(struct intc_source *source,
+ int enable_adj, int assert_adj)
+{
+ int enable_changed = 0;
+ int pending_changed = 0;
+ int old_pending;
+
+ if ((source->enable_count == source->enable_max) && (enable_adj == -1))
+ enable_changed = -1;
+
+ source->enable_count += enable_adj;
+
+ if (source->enable_count == source->enable_max)
+ enable_changed = 1;
+
+ source->asserted += assert_adj;
+
+ old_pending = source->pending;
+ source->pending = source->asserted &&
+ (source->enable_count == source->enable_max);
+
+ if (old_pending != source->pending)
+ pending_changed = 1;
+
+ if (pending_changed) {
+ if (source->pending) {
+ source->parent->pending++;
+#ifndef INTC_IRQS_DISABLED
+ if (source->parent->pending == 1)
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+#endif
+ }
+ else {
+ source->parent->pending--;
+#ifndef INTC_IRQS_DISABLED
+ if (source->parent->pending == 0)
+ cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+#endif
+ }
+ }
+
+ if (enable_changed || assert_adj || pending_changed) {
+#ifdef DEBUG_INTC_SOURCES
+ printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
+ source->parent->pending,
+ source->asserted,
+ source->enable_count,
+ source->enable_max,
+ source->vect,
+ source->asserted ? "asserted " :
+ assert_adj ? "deasserted" : "",
+ enable_changed == 1 ? "enabled " :
+ enable_changed == -1 ? "disabled " : "",
+ source->pending ? "pending" : "");
+#endif
+ }
+}
+
+unsigned int sh_intc_get_pending_vector(struct intc_desc *desc)
+{
+ unsigned int i;
+
+ /* slow: use a linked lists of pending sources instead */
+ /* wrong: take interrupt priority into account (one list per priority) */
+
+ for (i = 0; i < desc->nr_sources; i++) {
+ struct intc_source *source = desc->sources + i;
+
+ if (source->pending) {
+#ifdef DEBUG_INTC_SOURCES
+ printf("sh_intc: (%d) returning interrupt source 0x%x\n",
+ desc->pending, source->vect);
+#endif
+ return source->vect;
+ }
+ }
+
+ assert(0);
+}
+
#define INTC_MODE_NONE 0
#define INTC_MODE_DUAL_SET 1
#define INTC_MODE_DUAL_CLR 2
@@ -93,42 +175,24 @@ static void sh_intc_locate(struct intc_d
assert(0);
}
-static void sh_intc_toggle(struct intc_desc *desc, intc_enum id,
- int enable, int is_group)
+static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
+ int enable, int is_group)
{
struct intc_source *source = desc->sources + id;
- int old = source->enable_count;
if (!id)
return;
if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
-#ifdef DEBUG_INTC
+#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif
return;
}
- if (source->vect) {
- if (enable)
- source->enable_count++;
- else
- source->enable_count--;
+ if (source->vect)
+ sh_intc_toggle_source(source, enable ? 1 : -1, 0);
- if (source->enable_count == source->enable_max) {
-#ifdef DEBUG_INTC
- printf("sh_intc: enabling interrupt source %d -> 0x%04x\n",
- id, source->vect);
-#endif
- }
-
- if (old == source->enable_max) {
-#ifdef DEBUG_INTC
- printf("sh_intc: disabling interrupt source %d -> 0x%04x\n",
- id, source->vect);
-#endif
- }
- }
#ifdef DEBUG_INTC
else {
printf("setting interrupt group %d to %d\n", id, !!enable);
@@ -136,7 +200,7 @@ static void sh_intc_toggle(struct intc_d
#endif
if ((is_group || !source->vect) && source->next_enum_id) {
- sh_intc_toggle(desc, source->next_enum_id, enable, 1);
+ sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
}
#ifdef DEBUG_INTC
@@ -199,7 +263,7 @@ static void sh_intc_write(void *opaque,
printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
k, first, enum_ids[k], (unsigned int)mask);
#endif
- sh_intc_toggle(desc, enum_ids[k], value & mask, 0);
+ sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
}
*valuep = value;
@@ -308,7 +372,7 @@ void sh_intc_register_sources(struct int
if (s)
s->vect = vect->vect;
-#ifdef DEBUG_INTC
+#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
vect->enum_id, s->vect, s->enable_count, s->enable_max);
#endif
@@ -329,7 +393,7 @@ void sh_intc_register_sources(struct int
s->next_enum_id = gr->enum_ids[k];
}
-#ifdef DEBUG_INTC
+#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: registered group %d (%d/%d)\n",
gr->enum_id, s->enable_count, s->enable_max);
#endif
@@ -346,6 +410,7 @@ int sh_intc_init(struct intc_desc *desc,
{
unsigned int i;
+ desc->pending = 0;
desc->nr_sources = nr_sources;
desc->mask_regs = mask_regs;
desc->nr_mask_regs = nr_mask_regs;
@@ -358,6 +423,11 @@ int sh_intc_init(struct intc_desc *desc,
return -1;
memset(desc->sources, 0, i);
+ for (i = 0; i < desc->nr_sources; i++) {
+ struct intc_source *source = desc->sources + i;
+
+ source->parent = desc;
+ }
desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
sh_intc_writefn, desc);
--- 0001/hw/sh_intc.h
+++ work/hw/sh_intc.h 2007-11-09 19:14:17.000000000 +0900
@@ -35,9 +35,11 @@ struct intc_source {
unsigned short vect;
intc_enum next_enum_id;
- int asserted;
+ int asserted; /* emulates the interrupt signal line from device to intc */
int enable_count;
int enable_max;
+ int pending; /* emulates the result of signal and masking */
+ struct intc_desc *parent;
};
struct intc_desc {
@@ -49,9 +51,13 @@ struct intc_desc {
int nr_prio_regs;
int iomemtype;
+ int pending; /* number of interrupt sources that has pending set */
};
+unsigned int sh_intc_get_pending_vector(struct intc_desc *desc);
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
+void sh_intc_toggle_source(struct intc_source *source,
+ int enable_adj, int assert_adj);
void sh_intc_register_sources(struct intc_desc *desc,
struct intc_vect *vectors,
[-- Attachment #5: qemu-cvs-20071109c-sh-cpu-core-intc-glue.patch --]
[-- Type: application/octet-stream, Size: 3728 bytes --]
sh: connect cpu core to interrupt controller
This patch connects the cpu core to the interrupt controller.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
cpu-exec.c | 8 +++++++-
hw/sh7750.c | 2 ++
target-sh4/cpu.h | 3 +++
target-sh4/helper.c | 47 +++++++++++++++++++++++++++++++----------------
4 files changed, 43 insertions(+), 17 deletions(-)
--- 0001/cpu-exec.c
+++ work/cpu-exec.c 2007-11-09 19:56:16.000000000 +0900
@@ -517,7 +517,13 @@ int cpu_exec(CPUState *env1)
do_interrupt(env);
}
#elif defined(TARGET_SH4)
- /* XXXXX */
+ if ((interrupt_request & CPU_INTERRUPT_HARD)
+ && (!(env->sr & SR_BL))
+ && (((env->sr >> 4) & 0xf) != 0x0f)) {
+ env->exception_index = EXCP_SH_INTERRUPT |
+ sh_intc_get_pending_vector(env->intc_handle);
+ do_interrupt(env);
+ }
#elif defined(TARGET_ALPHA)
if (interrupt_request & CPU_INTERRUPT_HARD) {
do_interrupt(env);
--- 0003/hw/sh7750.c
+++ work/hw/sh7750.c 2007-11-09 19:18:27.000000000 +0900
@@ -550,6 +550,8 @@ SH7750State *sh7750_init(CPUSH4State * c
_INTC_ARRAY(vectors),
_INTC_ARRAY(groups));
+ cpu->intc_handle = &s->intc;
+
sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
s->periph_freq, serial_hds[1]);
--- 0001/target-sh4/cpu.h
+++ work/target-sh4/cpu.h 2007-11-09 19:18:27.000000000 +0900
@@ -121,6 +121,7 @@ typedef struct CPUSH4State {
int exception_index;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
+ void *intc_handle;
} CPUSH4State;
CPUSH4State *cpu_sh4_init(void);
@@ -163,4 +164,6 @@ enum {
#define MMUCR_AT (1<<0)
#define MMUCR_SV (1<<8)
+#define EXCP_SH_INTERRUPT 0x8000
+
#endif /* _CPU_SH4_H */
--- 0001/target-sh4/helper.c
+++ work/target-sh4/helper.c 2007-11-09 19:18:27.000000000 +0900
@@ -117,32 +117,47 @@ void do_interrupt(CPUState * env)
expname = "trapa";
break;
default:
- expname = "???";
- break;
+ if (env->exception_index & EXCP_SH_INTERRUPT)
+ expname = "interrupt";
+ else
+ expname = "???";
+ break;
}
fprintf(logfile, "exception 0x%03x [%s] raised\n",
env->exception_index, expname);
cpu_dump_state(env, logfile, fprintf, 0);
}
+ if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
+ printf("zzzzzzzzzzzz in delay slot!\n");
+ }
+
env->ssr = env->sr;
- env->spc = env->spc;
+ env->spc = env->pc;
env->sgr = env->gregs[15];
env->sr |= SR_BL | SR_MD | SR_RB;
- env->expevt = env->exception_index & 0x7ff;
- switch (env->exception_index) {
- case 0x040:
- case 0x060:
- case 0x080:
- env->pc = env->vbr + 0x400;
- break;
- case 0x140:
- env->pc = 0xa0000000;
- break;
- default:
- env->pc = env->vbr + 0x100;
- break;
+ if (env->exception_index & EXCP_SH_INTERRUPT) {
+ env->intevt = env->exception_index & 0x1fff;
+ env->pc = env->vbr + 0x600;
+ }
+ else {
+ env->expevt = env->exception_index & 0xfff;
+
+ switch (env->exception_index) {
+ case 0x000:
+ case 0x020:
+ case 0x140:
+ env->pc = 0xa0000000;
+ break;
+ case 0x040:
+ case 0x060:
+ env->pc = env->vbr + 0x400;
+ break;
+ default:
+ env->pc = env->vbr + 0x100;
+ break;
+ }
}
}
[-- Attachment #6: qemu-cvs-20071114-sh-timer-intc.patch --]
[-- Type: application/octet-stream, Size: 4914 bytes --]
sh_timer: add interrupt support
This patch adds interrupt support to the sh timer code.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
hw/sh.h | 8 ++++++++
hw/sh7750.c | 12 +++++++++---
hw/sh_timer.c | 32 ++++++++++++++++++--------------
vl.h | 6 ------
4 files changed, 35 insertions(+), 23 deletions(-)
--- 0002/hw/sh.h
+++ work/hw/sh.h 2007-11-14 19:39:18.000000000 +0900
@@ -8,4 +8,12 @@
void sh_serial_init (target_phys_addr_t base, int feat,
uint32_t freq, CharDriverState *chr);
+/* sh_timer.c */
+#define TMU012_FEAT_TOCR (1 << 0)
+#define TMU012_FEAT_3CHAN (1 << 1)
+#define TMU012_FEAT_EXTCLK (1 << 2)
+void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+ struct intc_source *ch0_irq, struct intc_source *ch1_irq,
+ struct intc_source *ch2_irq0, struct intc_source *ch2_irq1);
+
#endif /* __SH_H__ */
--- 0005/hw/sh7750.c
+++ work/hw/sh7750.c 2007-11-14 19:40:52.000000000 +0900
@@ -558,8 +558,11 @@ SH7750State *sh7750_init(CPUSH4State * c
tmu012_init(0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
- s->periph_freq);
-
+ s->periph_freq,
+ sh_intc_source(&s->intc, TMU0),
+ sh_intc_source(&s->intc, TMU1),
+ sh_intc_source(&s->intc, TMU2_TUNI),
+ sh_intc_source(&s->intc, TMU2_TICPI));
if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc,
@@ -577,7 +580,10 @@ SH7750State *sh7750_init(CPUSH4State * c
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
- tmu012_init(0x1e100000, 0, s->periph_freq);
+ tmu012_init(0x1e100000, 0, s->periph_freq,
+ sh_intc_source(&s->intc, TMU3),
+ sh_intc_source(&s->intc, TMU4),
+ NULL, NULL);
}
if (cpu_model & (SH_CPU_SH7751_ALL)) {
--- 0002/hw/sh_timer.c
+++ work/hw/sh_timer.c 2007-11-14 19:39:18.000000000 +0900
@@ -32,23 +32,23 @@ typedef struct {
uint32_t tcpr;
int freq;
int int_level;
+ int old_level;
int feat;
int enabled;
- qemu_irq irq;
+ struct intc_source *irq;
} sh_timer_state;
/* Check all active timers, and schedule the next timer interrupt. */
static void sh_timer_update(sh_timer_state *s)
{
-#if 0 /* not yet */
- /* Update interrupts. */
- if (s->int_level && (s->tcr & TIMER_TCR_UNIE)) {
- qemu_irq_raise(s->irq);
- } else {
- qemu_irq_lower(s->irq);
- }
-#endif
+ int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
+
+ if (new_level != s->old_level)
+ sh_intc_toggle_source(s->irq, 0, new_level ? 1 : -1);
+
+ s->old_level = s->int_level;
+ s->int_level = new_level;
}
uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
@@ -184,7 +184,7 @@ static void sh_timer_tick(void *opaque)
sh_timer_update(s);
}
-static void *sh_timer_init(uint32_t freq, int feat)
+static void *sh_timer_init(uint32_t freq, int feat, struct intc_source *irq)
{
sh_timer_state *s;
QEMUBH *bh;
@@ -197,6 +197,7 @@ static void *sh_timer_init(uint32_t freq
s->tcpr = 0xdeadbeef;
s->tcor = 0;
s->enabled = 0;
+ s->irq = irq;
bh = qemu_bh_new(sh_timer_tick, s);
s->timer = ptimer_init(bh);
@@ -304,7 +305,9 @@ static CPUWriteMemoryFunc *tmu012_writef
tmu012_write
};
-void tmu012_init(uint32_t base, int feat, uint32_t freq)
+void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+ struct intc_source *ch0_irq, struct intc_source *ch1_irq,
+ struct intc_source *ch2_irq0, struct intc_source *ch2_irq1)
{
int iomemtype;
tmu012_state *s;
@@ -313,10 +316,11 @@ void tmu012_init(uint32_t base, int feat
s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
s->base = base;
s->feat = feat;
- s->timer[0] = sh_timer_init(freq, timer_feat);
- s->timer[1] = sh_timer_init(freq, timer_feat);
+ s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
+ s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
if (feat & TMU012_FEAT_3CHAN)
- s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT);
+ s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
+ ch2_irq0); /* ch2_irq1 not supported */
iomemtype = cpu_register_io_memory(0, tmu012_readfn,
tmu012_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
--- 0002/vl.h
+++ work/vl.h 2007-11-14 19:39:18.000000000 +0900
@@ -1361,12 +1361,6 @@ typedef struct {
int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device);
-/* sh_timer.c */
-#define TMU012_FEAT_TOCR (1 << 0)
-#define TMU012_FEAT_3CHAN (1 << 1)
-#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(uint32_t base, int feat, uint32_t freq);
-
/* tc58128.c */
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
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