From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops
Date: Mon, 23 Sep 2024 12:10:42 +0200 [thread overview]
Message-ID: <aec8f70f-9a9c-4ce9-9d49-d3e895497f90@linaro.org> (raw)
In-Reply-To: <8f4fb8f4-508b-40f0-ac9e-f3f591b5aae5@linux.alibaba.com>
On 9/23/24 06:46, LIU Zhiwei wrote:
>
> On 2024/9/22 12:46, Richard Henderson wrote:
>> On 9/11/24 15:26, LIU Zhiwei wrote:
>>> @@ -2129,6 +2389,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>>> static void tcg_out_tb_start(TCGContext *s)
>>> {
>>> + s->riscv_cur_type = TCG_TYPE_COUNT;
>>> /* nothing to do */
>>> }
>>
>> I recently realized that the vector config is call-clobbered.
>> We need this reset as well in tcg_out_call_int(),
> OK.
>> and prepare_host_addr().
>>
>> In prepare_host_addr, place the reset just after the two calls to new_ldst_label().
>
> As slow path will also cal tcg_out_call_init, can we only reset after tcg_out_call_init?
No, because all slow path code is emitted out-of-line at the end of the TB. When we begin
generating code for he next TCGOp, we will not yet have called tcg_out_call_init.
Therefore we must recognize this possibility when generating the branch to the slow path.
r~
next prev parent reply other threads:[~2024-09-23 10:11 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-11 13:26 [PATCH v4 00/12] tcg/riscv: Add support for vector LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-11 18:34 ` Richard Henderson
2024-09-18 5:14 ` LIU Zhiwei
2024-09-18 10:14 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 02/12] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-11 18:41 ` Richard Henderson
2024-09-18 5:17 ` LIU Zhiwei
2024-09-18 10:11 ` Richard Henderson
2024-09-18 10:43 ` LIU Zhiwei
2024-09-18 14:27 ` Richard Henderson
2024-09-20 4:01 ` 0x48 Swung
2024-09-20 4:27 ` LIU Zhiwei
2024-09-20 14:26 ` LIU Zhiwei
2024-09-21 15:56 ` 0x48 Swung
2024-09-21 17:17 ` Daniel Henrique Barboza
2024-09-20 11:26 ` Daniel Henrique Barboza
2024-09-20 11:37 ` Markus Armbruster
2024-09-11 13:26 ` [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops LIU Zhiwei
2024-09-11 22:57 ` Richard Henderson
2024-09-22 4:46 ` Richard Henderson
2024-09-23 4:46 ` LIU Zhiwei
2024-09-23 10:10 ` Richard Henderson [this message]
2024-09-11 13:26 ` [PATCH v4 04/12] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-11 23:07 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 05/12] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 06/12] tcg/riscv: Implement vector cmp/cmpsel ops LIU Zhiwei
2024-09-11 23:14 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 07/12] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 08/12] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 09/12] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 10/12] tcg/riscv: Implement vector shi/s/v ops LIU Zhiwei
2024-09-11 23:15 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 11/12] tcg/riscv: Implement vector roti/v/x ops LIU Zhiwei
2024-09-11 23:24 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
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