From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e2kPT-0006iy-C0 for qemu-devel@nongnu.org; Thu, 12 Oct 2017 16:48:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e2kPO-000660-I6 for qemu-devel@nongnu.org; Thu, 12 Oct 2017 16:48:51 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:51144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e2kPO-00065k-Bm for qemu-devel@nongnu.org; Thu, 12 Oct 2017 16:48:46 -0400 Received: by mail-pf0-x236.google.com with SMTP id m63so6581158pfk.7 for ; Thu, 12 Oct 2017 13:48:46 -0700 (PDT) References: From: Richard Henderson Message-ID: Date: Thu, 12 Oct 2017 13:48:42 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stafford Horne , QEMU Development Cc: Openrisc , Richard Henderson On 08/22/2017 10:57 PM, Stafford Horne wrote: > Add OpenRISC Multicore PIC which handles inter processor interrupts > (IPI) between cores. In OpenRISC all device interrupts are routed to > each core enabling this device to be simple. > > Signed-off-by: Stafford Horne > --- > default-configs/or1k-softmmu.mak | 1 + > hw/intc/Makefile.objs | 1 + > hw/intc/ompic.c | 179 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 181 insertions(+) > create mode 100644 hw/intc/ompic.c Reviewed-by: Richard Henderson r~