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[176.184.18.96]) by smtp.gmail.com with ESMTPSA id df2-20020a5d5b82000000b0033d6c928a95sm8796319wrb.63.2024.02.22.06.47.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Feb 2024 06:47:21 -0800 (PST) Message-ID: Date: Thu, 22 Feb 2024 15:47:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/3] hw/i2c: smbus: Reset fixes Content-Language: en-US To: minyard@acm.org, Joe Komlodi Cc: venture@google.com, peter.maydell@linaro.org, qemu-devel@nongnu.org References: <20240220211123.2664977-1-komlodi@google.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240220211123.2664977-1-komlodi@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Joe, On 20/2/24 22:11, Joe Komlodi wrote: > Changelog: > This series adds some resets for SMBus and for the I2C core. Along with > it, we make SMBus slave error printing a little more helpful. > > These reset issues were very infrequent, they would maybe occur in 1 out > of hundreds of resets in our testing, but the way they happen is pretty > straightforward. > > Basically as long as a reset happens in the middle of a transaction, the > state of the old transaction would still partially be there after the > reset. Once a new transaction comes in, the partial stale state can > cause the new transaction to incorrectly fail. Sorry for jumping late, at v4. I'm a bit confused by this series. - AFAICT there is no in-band or RESET line with I2C, but the AN10216 document mentions: I2C Bus recovery • Typical case is when masters fails when doing a read operation in a slave • SDA line is then non usable anymore because of the “Slave-Transmitter” mode. • Methods to recover the SDA line are: – Reset the slave device (assuming the device has a Reset pin) – Use a bus recovery sequence to leave the “Slave- Transmitter” mode • Bus recovery sequence is done as following: 1 - Send 9 clock pulses on SCL line 2 - Ask the master to keep SDA High until the “Slave- Transmitter” releases the SDA line to perform the ACK operation 3 - Keeping SDA High during the ACK means that the “Master-Receiver” does not acknowledge the previous byte receive 4 - The “Slave-Transmitter” then goes in an idle state 5 - The master then sends a STOP command initializing completely the bus - For SMBus Specification Version 2.0: 3.1.4.2 Power-on reset SMBus devices detect a power-on event in one of three ways: • By detecting that power is being applied to the device, • By an external reset signal that is being asserted or • For self-powered or always powered devices, by detecting that the SMBus is active (clock and data lines have gone high after being low for more than 2 1/2 seconds). Questions: - Is the first patch "hw/i2c: core: Add reset" really for I2C? Otherwise we could expand smbus form i2cbus, and have this reset only for smbus. - Should we model the "I2C bus recovery sequence" before triggering reset? - Shouldn't we model the smbus 2.5s timeout before triggering the reset? Thanks, Phil.