From: Eric Auger <eric.auger@redhat.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com,
ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com,
mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com,
wangzhou1@hisilicon.com, jiangkunkun@huawei.com,
jonathan.cameron@huawei.com, zhangfei.gao@linaro.org
Subject: Re: [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices
Date: Thu, 5 Jun 2025 11:57:36 +0200 [thread overview]
Message-ID: <af1f7082-dc4b-4f44-9b85-aa6ba9221e71@redhat.com> (raw)
In-Reply-To: <20250602154110.48392-4-shameerali.kolothum.thodi@huawei.com>
Hi Shameer,
On 6/2/25 5:41 PM, Shameer Kolothum wrote:
> With the soon to be introduced user-creatable SMMUv3 devices for
> virt, it is possible to have multiple SMMUv3 devices associated
> with different PCIe root complexes.
>
> Update IORT nodes accordingly.
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
> hw/arm/virt-acpi-build.c | 54 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index bd26853ef6..b4ff71b8b7 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -43,6 +43,7 @@
> #include "hw/acpi/generic_event_device.h"
> #include "hw/acpi/tpm.h"
> #include "hw/acpi/hmat.h"
> +#include "hw/arm/smmuv3.h"
> #include "hw/pci/pcie_host.h"
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_bus.h"
> @@ -288,6 +289,54 @@ get_smmuv3_legacy_dev(VirtMachineState *vms, void *opaque)
> g_array_append_val(sdev_blob, sdev);
> }
>
> +static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b)
> +{
> + AcpiIortSMMUv3Dev *sdev_a = (AcpiIortSMMUv3Dev *)a;
> + AcpiIortSMMUv3Dev *sdev_b = (AcpiIortSMMUv3Dev *)b;
> + AcpiIortIdMapping *map_a = &g_array_index(sdev_a->idmaps,
> + AcpiIortIdMapping, 0);
> + AcpiIortIdMapping *map_b = &g_array_index(sdev_b->idmaps,
> + AcpiIortIdMapping, 0);
> + return map_a->input_base - map_b->input_base;
> +}
> +
> +static int get_smmuv3_devices(Object *obj, void *opaque)
> +{
> + VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
> + GArray *sdev_blob = opaque;
> + AcpiIortIdMapping idmap;
> + PlatformBusDevice *pbus;
> + AcpiIortSMMUv3Dev sdev;
> + int min_bus, max_bus;
> + SysBusDevice *sbdev;
> + PCIBus *bus;
> +
> + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) {
> + return 0;
> + }
> +
> + bus = PCI_BUS(object_property_get_link(obj, "primary-bus", &error_abort));
> + if (!bus) {
> + return 0;
> + }
can it happen after patch 1?
> +
> + pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
> + sbdev = SYS_BUS_DEVICE(obj);
> + sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> + sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;
> + sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);
> + sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];
> + sdev.irq += ARM_SPI_BASE;
> +
> + pci_bus_range(bus, &min_bus, &max_bus);
> + sdev.idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
> + idmap.input_base = min_bus << 8,
> + idmap.id_count = (max_bus - min_bus + 1) << 8,
> + g_array_append_val(sdev.idmaps, idmap);
> + g_array_append_val(sdev_blob, sdev);
> + return 0;
> +}
> +
> /*
> * Input Output Remapping Table (IORT)
> * Conforms to "IO Remapping Table System Software on ARM Platforms",
> @@ -319,6 +368,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> */
> sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, 0);
> g_array_sort(sdev->idmaps, iort_idmap_compare);
> + } else {
> + object_child_foreach_recursive(object_get_root(),
> + get_smmuv3_devices, smmuv3_devs);
> + /* Sort the smmuv3 devices(if any) by smmu idmap input_base */
> + g_array_sort(smmuv3_devs, smmuv3_dev_idmap_compare);
Given the gorwing complexity of the IDMAP computation computation I
would suggest to add some IDMAP examples either in comment or commit msg
to illustrate how the idmaps look like (similar to what can be found in
the IORT spec).
Thanks
Eric
> }
>
> num_smmus = smmuv3_devs->len;
next prev parent reply other threads:[~2025-06-05 9:58 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-02 15:41 [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association Shameer Kolothum via
2025-06-05 9:13 ` Eric Auger
2025-06-05 9:53 ` Eric Auger
2025-06-05 10:02 ` Eric Auger via
2025-06-05 11:15 ` Shameerali Kolothum Thodi via
2025-06-05 10:55 ` Igor Mammedov
2025-06-05 11:29 ` Shameerali Kolothum Thodi via
2025-06-05 12:19 ` Igor Mammedov
2025-06-05 12:36 ` Shameerali Kolothum Thodi via
2025-06-05 13:05 ` Igor Mammedov
2025-06-02 15:41 ` [PATCH v3 2/6] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-05 9:39 ` Eric Auger
2025-06-05 11:10 ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-05 9:57 ` Eric Auger [this message]
2025-06-05 11:14 ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 4/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 5/6] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 6/6] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-05 12:45 ` Eric Auger
2025-06-05 2:02 ` [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Nathan Chen
2025-06-05 2:34 ` Donald Dutile
2025-06-05 17:58 ` Nathan Chen
2025-06-05 20:58 ` Donald Dutile
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