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[176.184.30.254]) by smtp.gmail.com with ESMTPSA id v10-20020adfe28a000000b003063a1cdaf2sm1780166wri.48.2023.05.25.06.17.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 May 2023 06:17:49 -0700 (PDT) Message-ID: Date: Thu, 25 May 2023 15:17:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 09/12] hw/char/pl011: Check if transmitter is enabled Content-Language: en-US To: Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, Paolo Bonzini , qemu-arm@nongnu.org, Evgeny Iakovlev , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= References: <20230522153144.30610-1-philmd@linaro.org> <20230522153144.30610-10-philmd@linaro.org> <87zg5stvyi.fsf@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 25/5/23 14:55, Peter Maydell wrote: > On Thu, 25 May 2023 at 13:52, Alex Bennée wrote: >> >> >> Peter Maydell writes: >> >>> On Mon, 22 May 2023 at 16:32, Philippe Mathieu-Daudé wrote: >>>> >>>> Do not transmit characters when UART or transmitter are disabled. >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé >>> >>> Last time somebody tried to add checks on the tx/rx enable bits >>> for the PL011 it broke 'make check' because the hand-rolled >>> UART code in boot-serial-test and migration-test doesn't >>> set up the UART control register strictly correctly: >>> >>> https://lore.kernel.org/qemu-devel/CAFEAcA8ZDmjP7G0eVpxcB1jiSGarZAbqPV0xr5WquR213mBUBg@mail.gmail.com/ Hmm I ran 'make check-qtest' my build directory only targets aarch64, I probably missed the arm (32-bit) tests :/ >>> Given that imposing these checks doesn't help anything >>> much and might break naive bare-metal tested-only-on-QEMU >>> code, is it worthwhile ? >> >> Surely we aim to be a correct model so the fix should be in our naive >> and incorrect code? > > In our own test suites, sure -- we should probably fix that > even if we don't change the PL011 model to require it. > But if we let this kind of thing get past us in our own testsuite, > it suggests there's probably a lot of similar naive code out > there in the world -- these Arm boards with PL011s are pretty > commonly used for "my first bare metal assembly program" stuff > and there's a lot of cargo-culting of how to do things like > serial output, and programs that were never tested on any > real hardware... OK. I'll add a comment, keep the current behavior when TX is disabled, but add a GUEST_ERROR log message.