Re: [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 22/2/25 19:17, Richard Henderson wrote:
> On 2/20/25 15:27, Philippe Mathieu-Daudé wrote:
>> On 5/5/23 23:24, Richard Henderson wrote:
>>> The port currently does not support "oversize" guests, which
>>> means riscv32 can only target 32-bit guests.  We will soon be
>>> building TCG once for all guests.  This implies that we can
>>> only support riscv64.
>>>
>>> Since all Linux distributions target riscv64 not riscv32,
>>> this is not much of a restriction and simplifies the code.
>>>
>>> The brcond2 and setcond2 opcodes are exclusive to 32-bit hosts,
>>> so we can and should remove the stubs.
>>>
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>>   tcg/riscv/tcg-target-con-set.h |   8 --
>>>   tcg/riscv/tcg-target.h         |  22 ++--
>>>   tcg/riscv/tcg-target.c.inc     | 232 +++++++++------------------------
>>>   3 files changed, 72 insertions(+), 190 deletions(-)
>>
>>
>>> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
>>> index 0deb33701f..dddf2486c1 100644
>>> --- a/tcg/riscv/tcg-target.h
>>> +++ b/tcg/riscv/tcg-target.h
>>> @@ -25,11 +25,14 @@
>>>   #ifndef RISCV_TCG_TARGET_H
>>>   #define RISCV_TCG_TARGET_H
>>> -#if __riscv_xlen == 32
>>> -# define TCG_TARGET_REG_BITS 32
>>> -#elif __riscv_xlen == 64
>>> -# define TCG_TARGET_REG_BITS 64
>>> +/*
>>> + * We don't support oversize guests.
>>> + * Since we will only build tcg once, this in turn requires a 64-bit 
>>> host.
>>> + */
>>> +#if __riscv_xlen != 64
>>> +#error "unsupported code generation mode"
>>>   #endif
>>> +#define TCG_TARGET_REG_BITS 64
>>>   #define TCG_TARGET_INSN_UNIT_SIZE 4
>>>   #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
>>> @@ -83,13 +86,8 @@ typedef enum {
>>>   #define TCG_TARGET_STACK_ALIGN          16
>>>   #define TCG_TARGET_CALL_STACK_OFFSET    0
>>>   #define TCG_TARGET_CALL_ARG_I32         TCG_CALL_ARG_NORMAL
>>> -#if TCG_TARGET_REG_BITS == 32
>>> -#define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_EVEN
>>> -#define TCG_TARGET_CALL_ARG_I128        TCG_CALL_ARG_EVEN
>>> -#else
>>>   #define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_NORMAL
>>>   #define TCG_TARGET_CALL_ARG_I128        TCG_CALL_ARG_NORMAL
>>> -#endif
>>>   #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_NORMAL
>>>   /* optional instructions */
>>> @@ -106,8 +104,8 @@ typedef enum {
>>>   #define TCG_TARGET_HAS_sub2_i32         1
>>>   #define TCG_TARGET_HAS_mulu2_i32        0
>>>   #define TCG_TARGET_HAS_muls2_i32        0
>>> -#define TCG_TARGET_HAS_muluh_i32        (TCG_TARGET_REG_BITS == 32)
>>> -#define TCG_TARGET_HAS_mulsh_i32        (TCG_TARGET_REG_BITS == 32)
>>> +#define TCG_TARGET_HAS_muluh_i32        0
>>> +#define TCG_TARGET_HAS_mulsh_i32        0
>>
>> Should have we squashed the following with these changes?
> 
> Yes, mulsh_i32 is not reachable anymore.  At this point I'll just leave 
> this cleanup to conversion of mulsh to TCGOutOpBinary.

Sure, I was not planing to ask for another patch, but trying to see if
I was correctly understanding your conversion.

Thanks,

Phil.