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Tue, 30 Jun 2026 02:51:07 -0700 (PDT) Received: from localhost ([64.186.250.142]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30ee300b286sm6662226eec.12.2026.06.30.02.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 02:51:07 -0700 (PDT) Date: Tue, 30 Jun 2026 17:51:04 +0800 From: Chao Liu To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, andrew.jones@oss.qualcomm.com, Palmer Dabbelt , Tao Tang , Fabiano Rosas , Laurent Vivier , Paolo Bonzini Subject: Re: [PATCH 2/2] hw/riscv/riscv-iommu.c: fault when !PTE_U and no priv access Message-ID: References: <20260629121334.567587-1-daniel.barboza@oss.qualcomm.com> <20260629121334.567587-3-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260629121334.567587-3-daniel.barboza@oss.qualcomm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1343; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jun 29, 2026 at 09:13:34AM +0800, Daniel Henrique Barboza wrote: > All IOMMU accesses are assumed to be user mode unless told otherwise, > i.e. we have a process_id. In case we have a non-user mode leaf PTE > (PTE_U isn't set) and we are running in user mode, we need to throw a > fault. > > This also reflects on qos-riscv-iommu tests: the tests always run in > user mode so our PTEs must have PTE_U (bit 0x10) set. > > Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3553 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu > --- > hw/riscv/riscv-iommu.c | 8 ++++++++ > tests/qtest/libqos/qos-riscv-iommu.h | 4 ++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index 453601d7a5..e6d2ca94bc 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -297,6 +297,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, > G_STAGE = 1, > } pass; > MemTxResult ret; > + bool pv = !!ctx->process_id; > > satp = get_field(ctx->satp, RISCV_IOMMU_ATP_MODE_FIELD); > gatp = get_field(ctx->gatp, RISCV_IOMMU_ATP_MODE_FIELD); > @@ -470,6 +471,13 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, > break; /* Invalid PTE */ > } else if (pte & PTE_RESERVED(false)) { > break; /* Reserved PTE bits set */ > + } else if (!(pte & PTE_U) && !pv) { > + /* > + * All accesses are assumed to be User mode unless > + * process_id is valid (pv). In case we have a > + * non-user mode PTE and !pv we need to fault. > + */ > + break; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > base = PPN_PHYS(ppn); /* Inner PTE, continue walking */ > } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { > diff --git a/tests/qtest/libqos/qos-riscv-iommu.h b/tests/qtest/libqos/qos-riscv-iommu.h > index 90e69a5d73..c218e9d66d 100644 > --- a/tests/qtest/libqos/qos-riscv-iommu.h > +++ b/tests/qtest/libqos/qos-riscv-iommu.h > @@ -54,8 +54,8 @@ > * PTE masks for RISC-V IOMMU page tables. > * Values match PTE_V, PTE_R, PTE_W, PTE_A, PTE_D in target/riscv/cpu_bits.h > */ > -#define QRIOMMU_NON_LEAF_PTE_MASK 0x001 /* PTE_V */ > -#define QRIOMMU_LEAF_PTE_RW_MASK 0x0c7 /* V|R|W|A|D */ > +#define QRIOMMU_NON_LEAF_PTE_MASK 0x011 /* PTE_V | PTE_U */ > +#define QRIOMMU_LEAF_PTE_RW_MASK 0x0d7 /* V | R | W | A | D | PTE_U */ > #define QRIOMMU_PTE_PPN_MASK 0x003ffffffffffc00ull > > /* Address-space base offset for test tables */ > -- > 2.43.0 >