[Qemu-devel] [PATCH 0/3] MIPS: GDB register width fix / ABI configuration rework

[Qemu-devel] [PATCH 0/3] MIPS: GDB register width fix / ABI configuration rework

[Maciej W. Rozycki]

Hi,

 This mini patch series corrects some misguided assumptions in QEMU's MIPS 
processor selection while also adding another configuration to support a 
missing ABI-processor combination, and then corrects register widths used 
by the GDB stub so as to match the processor selected (for the system 
emulation mode) or the ABI selected (for the user emulation mode), to 
match GDB's expectations.

 Ideally we should be using XML register descriptions to communicate 
hardware (raw) register widths, but GDB is not yet prepared for it, not 
for the system emulation mode, that is.  This rework does not preclude 
such an improvement in the future once GDB is capable enough, which would 
apply directly on top as the registers widths set here are the correct 
ones for each of the configurations concerned.  Without XML support the 
correct processor type has to be selected in GDB manually such as to 
match one selected in QEMU for emulation; this does note have to be an 
exact match, it only has to be close enough.

 Also ideally we'd support two configurations only, mips|mipsel and 
mips64|mips64el, and be able to load any compatible ELF executable, 
either 32-bit i.e. ELF32 non-ABI2 (with both configurations) or 64-bit 
i.e. ELF64 or ELF32 ABI2 (with the latter configuration only), into the 
same binary, in the user emulation mode case also selecting the correct 
ABI and consequently syscall environment on the fly, one of o32 (again 
with both configurations), n32 (with the latter configuration only) and 
n64 (likewise).  Again, this can be done in the future as resources 
permit as this appears to me it would be a major effort.

 The current arrangement for the existing QEMU configurations is as 
follows:

1. mips|mipsel       -- 32-bit processors only, o32 user-mode and GDB ABI,

2. mipsn32|mipsn32el -- 32-bit and 64-bit processors, n32 user-mode and 
                        n64 GDB ABI,

3. mips64|mips64el   -- 32-bit and 64-bit processors, n64 user-mode and 
                        GDB ABI.

 I have made no changes to the first configuration, except from providing 
an extra TARGET_MIPS32 macro to make a separate selection of 32-bit 
processors possible.

 Configurations #2 and #3 suffer from the fundamental problem that both 
the n32 and the n64 ABI require a 64-bit processor.  These configurations 
are therefore buggy -- no 32-bit processor should be available for them.  
Additionally we're missing an o32 ABI configuration that would permit 
64-bit processors, as that ABI is in fact compatible with such processors.  
Finally for mipsn32|mipsn32el the GDB RSP stub's ABI does not match the 
name of the configuration and also the user-mode ABI.

 I have therefore made changes to arrange for the following 
configurations:

1. mips|mipsel       -- 32-bit processors only, o32 user-mode and GDB ABI,

2. mips64|mips64el   -- 32-bit and 64-bit processors, o32 user-mode and 
                        GDB ABI,

3. mipsn32|mipsn32el -- 64-bit processors only, n32 user-mode and GDB ABI,

4. mipsn64|mipsn64el -- 64-bit processors only, n64 user-mode and GDB ABI.

I consider the choice of target names, and in particular the change of the 
semantics of "mips64|mips64el", a starting point for discussion.  I think 
the choice I made is about the most natural, an alternative might be 
embedding the name of the ABI into all targets, e.g.:

1. mipso32|mipso32el,

2. mips64o32|mips64o32el,

3. mips64n32|mips64n32el,

4. mips64n64|mips64n64el.

 We might consider discarding configuration #1 altogether as redundant, 
but my understanding is we have it mainly for performance reasons as it 
makes all internal target data types at most 32-bit wide, that has a 
code/data size benefit and also, on 32-bit hosts, processing time benefit.

 Configuration #2 is OTOH important to be able to use 32-bit features, 
regularly available to o32 programs, of these 64-bit processors that have 
no 32-bit counterparts.  In particular legacy MIPS architecture 
implementations and their properties such as the CP1.FCSR.FS bit of the 
R4000 processor for 32-bit MIPS III software, or the MIPS IV instruction 
subset of the VR5432 processor for 32-bit MIPS IV software.  It may be of 
a little bit less importance for contemporary MIPS architecture 
implementations that have more symmetry with the existence of the MIPS32 
and MIPS64 flavours in parallel, but I think this still makes sense for 
consistency if nothing else.

 Additionally I made clean-ups throughout, including but not limited to 
tying up some ABI-dependent properties to the respective ABI macros rather 
than the 64-bit configuration macro.

 These changes were validated as a side effect of the IEEE 754-2008 
updates posted recently, that were regression-tested with this patch set 
already applied.

 Comments?

  Maciej

[Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Maciej W. Rozycki]

Mechanically add new n32/n64 configuration files copying the relevant 
preexisting ones, fixing the system emulation configuration build, that 
breaks due to the lack of the respective configuration files, for the 
`mipsn32' and `mipsn32el' targets on this occasion as well.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
 To be applied first so as not to break the build and consequently 
bisection with the configuration changes posted next.

  Maciej

qemu-mips-configs.diff
Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn32-softmmu.mak	2014-11-01 04:54:58.247518643 +0000
@@ -0,0 +1,36 @@
+# Default configuration for mipsn32-softmmu
+
+include pci.mak
+include sound.mak
+include usb.mak
+CONFIG_ESP=y
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
+CONFIG_VGA_ISA=y
+CONFIG_VGA_ISA_MM=y
+CONFIG_VGA_CIRRUS=y
+CONFIG_VMWARE_VGA=y
+CONFIG_SERIAL=y
+CONFIG_PARALLEL=y
+CONFIG_I8254=y
+CONFIG_PCSPK=y
+CONFIG_PCKBD=y
+CONFIG_FDC=y
+CONFIG_ACPI=y
+CONFIG_APM=y
+CONFIG_I8257=y
+CONFIG_PIIX4=y
+CONFIG_IDE_ISA=y
+CONFIG_IDE_PIIX=y
+CONFIG_NE2000_ISA=y
+CONFIG_RC4030=y
+CONFIG_DP8393X=y
+CONFIG_DS1225Y=y
+CONFIG_MIPSNET=y
+CONFIG_PFLASH_CFI01=y
+CONFIG_G364FB=y
+CONFIG_I8259=y
+CONFIG_JAZZ_LED=y
+CONFIG_MC146818RTC=y
+CONFIG_ISA_TESTDEV=y
+CONFIG_EMPTY_SLOT=y
Index: qemu-git-trunk/default-configs/mipsn32el-softmmu.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn32el-softmmu.mak	2014-11-01 04:55:10.747732265 +0000
@@ -0,0 +1,39 @@
+# Default configuration for mipsn32el-softmmu
+
+include pci.mak
+include sound.mak
+include usb.mak
+CONFIG_ESP=y
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
+CONFIG_VGA_ISA=y
+CONFIG_VGA_ISA_MM=y
+CONFIG_VGA_CIRRUS=y
+CONFIG_VMWARE_VGA=y
+CONFIG_SERIAL=y
+CONFIG_PARALLEL=y
+CONFIG_I8254=y
+CONFIG_PCSPK=y
+CONFIG_PCKBD=y
+CONFIG_FDC=y
+CONFIG_ACPI=y
+CONFIG_APM=y
+CONFIG_I8257=y
+CONFIG_PIIX4=y
+CONFIG_IDE_ISA=y
+CONFIG_IDE_PIIX=y
+CONFIG_IDE_VIA=y
+CONFIG_NE2000_ISA=y
+CONFIG_RC4030=y
+CONFIG_DP8393X=y
+CONFIG_DS1225Y=y
+CONFIG_MIPSNET=y
+CONFIG_PFLASH_CFI01=y
+CONFIG_FULONG=y
+CONFIG_G364FB=y
+CONFIG_I8259=y
+CONFIG_JAZZ_LED=y
+CONFIG_MC146818RTC=y
+CONFIG_VT82C686=y
+CONFIG_ISA_TESTDEV=y
+CONFIG_EMPTY_SLOT=y
Index: qemu-git-trunk/default-configs/mipsn64-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64-linux-user.mak	2014-10-30 14:24:05.878953747 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64-linux-user
Index: qemu-git-trunk/default-configs/mipsn64-softmmu.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64-softmmu.mak	2014-11-01 04:55:27.248299838 +0000
@@ -0,0 +1,36 @@
+# Default configuration for mipsn64-softmmu
+
+include pci.mak
+include sound.mak
+include usb.mak
+CONFIG_ESP=y
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
+CONFIG_VGA_ISA=y
+CONFIG_VGA_ISA_MM=y
+CONFIG_VGA_CIRRUS=y
+CONFIG_VMWARE_VGA=y
+CONFIG_SERIAL=y
+CONFIG_PARALLEL=y
+CONFIG_I8254=y
+CONFIG_PCSPK=y
+CONFIG_PCKBD=y
+CONFIG_FDC=y
+CONFIG_ACPI=y
+CONFIG_APM=y
+CONFIG_I8257=y
+CONFIG_PIIX4=y
+CONFIG_IDE_ISA=y
+CONFIG_IDE_PIIX=y
+CONFIG_NE2000_ISA=y
+CONFIG_RC4030=y
+CONFIG_DP8393X=y
+CONFIG_DS1225Y=y
+CONFIG_MIPSNET=y
+CONFIG_PFLASH_CFI01=y
+CONFIG_G364FB=y
+CONFIG_I8259=y
+CONFIG_JAZZ_LED=y
+CONFIG_MC146818RTC=y
+CONFIG_ISA_TESTDEV=y
+CONFIG_EMPTY_SLOT=y
Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64el-linux-user.mak	2014-10-30 14:24:05.878953747 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64el-linux-user
Index: qemu-git-trunk/default-configs/mipsn64el-softmmu.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64el-softmmu.mak	2014-11-01 04:55:39.748239599 +0000
@@ -0,0 +1,39 @@
+# Default configuration for mipsn64el-softmmu
+
+include pci.mak
+include sound.mak
+include usb.mak
+CONFIG_ESP=y
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
+CONFIG_VGA_ISA=y
+CONFIG_VGA_ISA_MM=y
+CONFIG_VGA_CIRRUS=y
+CONFIG_VMWARE_VGA=y
+CONFIG_SERIAL=y
+CONFIG_PARALLEL=y
+CONFIG_I8254=y
+CONFIG_PCSPK=y
+CONFIG_PCKBD=y
+CONFIG_FDC=y
+CONFIG_ACPI=y
+CONFIG_APM=y
+CONFIG_I8257=y
+CONFIG_PIIX4=y
+CONFIG_IDE_ISA=y
+CONFIG_IDE_PIIX=y
+CONFIG_IDE_VIA=y
+CONFIG_NE2000_ISA=y
+CONFIG_RC4030=y
+CONFIG_DP8393X=y
+CONFIG_DS1225Y=y
+CONFIG_MIPSNET=y
+CONFIG_PFLASH_CFI01=y
+CONFIG_FULONG=y
+CONFIG_G364FB=y
+CONFIG_I8259=y
+CONFIG_JAZZ_LED=y
+CONFIG_MC146818RTC=y
+CONFIG_VT82C686=y
+CONFIG_ISA_TESTDEV=y
+CONFIG_EMPTY_SLOT=y

[Qemu-devel] [PATCH 2/3] target-mips: Rework ABIs to allow all required configurations

[Maciej W. Rozycki]

Rework the MIPS ABIs and CPU emulations available according to the 
following target list:

- mips|mipsel       -- 32-bit CPUs only, o32 user and GDB ABI,

- mips64|mips64el   -- 32-bit and 64-bit CPUs, o32 user and GDB ABI,

- mipsn32|mipsn32el -- 64-bit CPUs only, n32 user and GDB ABI,

- mipsn64|mipsn64el -- 64-bit CPUs only, n64 user and GDB ABI.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
qemu-mips64-abis.diff
Index: qemu-git-trunk/bsd-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/bsd-user/elfload.c	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/bsd-user/elfload.c	2014-11-21 09:43:29.957674289 +0000
@@ -381,7 +381,7 @@ static inline void init_thread(struct ta
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
Index: qemu-git-trunk/configure
===================================================================
--- qemu-git-trunk.orig/configure	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/configure	2014-11-21 10:05:07.598353639 +0000
@@ -4982,7 +4982,7 @@ target_name=`echo $target | cut -d '-' -
 target_bigendian="no"
 
 case "$target_name" in
-  armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  armeb|lm32|m68k|microblaze|mips|mips64|mipsn32|mipsn64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
@@ -5057,17 +5057,28 @@ case "$target_name" in
   ;;
   mips|mipsel)
     TARGET_ARCH=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
     echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
   ;;
+  mips64|mips64el)
+    TARGET_ARCH=mips64
+    TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
+    echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
+    echo "TARGET_ABI32=y" >> $config_target_mak
+  ;;
   mipsn32|mipsn32el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak
     echo "TARGET_ABI32=y" >> $config_target_mak
   ;;
-  mips64|mips64el)
+  mipsn64|mipsn64el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
   ;;
   tricore)
Index: qemu-git-trunk/include/exec/poison.h
===================================================================
--- qemu-git-trunk.orig/include/exec/poison.h	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/include/exec/poison.h	2014-11-21 09:43:30.458929160 +0000
@@ -13,7 +13,11 @@
 #pragma GCC poison TARGET_LM32
 #pragma GCC poison TARGET_M68K
 #pragma GCC poison TARGET_MIPS
+#pragma GCC poison TARGET_MIPS32
 #pragma GCC poison TARGET_MIPS64
+#pragma GCC poison TARGET_ABI_MIPSO32
+#pragma GCC poison TARGET_ABI_MIPSN32
+#pragma GCC poison TARGET_ABI_MIPSN64
 #pragma GCC poison TARGET_OPENRISC
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPCEMB
Index: qemu-git-trunk/linux-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/linux-user/elfload.c	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/linux-user/elfload.c	2014-11-21 09:43:30.458929160 +0000
@@ -875,7 +875,7 @@ static void elf_core_copy_regs(target_el
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
@@ -896,10 +896,10 @@ typedef target_elf_greg_t target_elf_gre
 
 /* See linux kernel: arch/mips/include/asm/reg.h.  */
 enum {
-#ifdef TARGET_MIPS64
-    TARGET_EF_R0 = 0,
-#else
+#ifdef TARGET_ABI_MIPSO32
     TARGET_EF_R0 = 6,
+#else
+    TARGET_EF_R0 = 0,
 #endif
     TARGET_EF_R26 = TARGET_EF_R0 + 26,
     TARGET_EF_R27 = TARGET_EF_R0 + 27,
Index: qemu-git-trunk/linux-user/main.c
===================================================================
--- qemu-git-trunk.orig/linux-user/main.c	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/linux-user/main.c	2014-11-21 09:43:30.957592635 +0000
@@ -3928,7 +3928,7 @@ int main(int argc, char **argv, char **e
         cpu_model = "Fujitsu MB86904";
 #endif
 #elif defined(TARGET_MIPS)
-#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+#ifdef TARGET_MIPS64
         cpu_model = "5KEf";
 #else
         cpu_model = "24Kf";
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c	2014-11-21 09:34:54.000000000 +0000
+++ qemu-git-trunk/target-mips/translate_init.c	2014-11-21 09:43:30.957592635 +0000
@@ -107,6 +107,7 @@ struct mips_def_t {
 /* MIPS CPU definitions */
 static const mips_def_t mips_defs[] =
 {
+#if defined(TARGET_MIPS32)
     {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
@@ -421,6 +422,7 @@ static const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
         .mmu_type = MMU_TYPE_R4000,
     },
+#endif
 #if defined(TARGET_MIPS64)
     {
         .name = "R4000",

[Qemu-devel] [PATCH 3/3] target-mips: Set GDB register widths correctly

[Maciej W. Rozycki]

Set register widths in the GDB stub as follows:

- for the system emulation mode -- to the native register size of the 
  processor selected, any MIPS I, MIPS II or MIPS32 (any revision) 
  processor will have 32-bit general purpose registers and any MIPS III, 
  MIPS IV or MIPS64 (again, any revision) will have 64-bit general 
  purpose registers,

- for the user emulation mode -- to the register size defined by the 
  ABI, that is the emulation of the o32 ABI will have 32-bit general 
  purpose registers and the emulation of the n32 and n64 ABIs will have 
  64-bit general purpose registers.

With the the user emulation mode, the o32 ABI and a 64-bit processor 
selected handle native 64-bit registers such that on reads they are 
truncated to low 32 bits only and on writes the 32-bit value stored is 
sign-extended from bit #31, which is how hardware instructions supported 
with the o32 ABI have been defined in the architecture.

Also correctly wrap the address space in the 32-bit o32 and n32 ABIs by 
sign-extending any addresses processed from bit #31, matching how the 
hardware operates in the user mode according to CP0.Status.UX == 0 and 
CP0.Status.PX == 0 (for o32) and CP0.Status.UX == 0 and CP0.Status.PX == 
1 (for n32).  This is also how GDB works operating on real processors in 
conjunction with JTAG hardware and associated debug-mode firmware across 
all execution modes.

As a side effect fix the case where registers are presented as 64-bit 
quantities while talking to a 32-bit processor.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
qemu-mips-regsize.diff
Index: qemu-git-trunk/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/gdbstub.c	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/gdbstub.c	2014-12-05 18:41:00.358928442 +0000
@@ -789,7 +789,7 @@ static int gdb_handle_packet(GDBState *s
         break;
     case 'c':
         if (*p != '\0') {
-            addr = strtoull(p, (char **)&p, 16);
+            addr = target_address(s->c_cpu, strtoull(p, (char **)&p, 16));
             gdb_set_cpu_pc(s, addr);
         }
         s->signal = 0;
@@ -875,7 +875,7 @@ static int gdb_handle_packet(GDBState *s
         break;
     case 's':
         if (*p != '\0') {
-            addr = strtoull(p, (char **)&p, 16);
+            addr = target_address(s->c_cpu, strtoull(p, (char **)&p, 16));
             gdb_set_cpu_pc(s, addr);
         }
         cpu_single_step(s->c_cpu, sstep_flags);
@@ -930,7 +930,7 @@ static int gdb_handle_packet(GDBState *s
         put_packet(s, "OK");
         break;
     case 'm':
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, NULL, 16);
@@ -942,7 +942,7 @@ static int gdb_handle_packet(GDBState *s
         }
         break;
     case 'M':
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, (char **)&p, 16);
@@ -987,7 +987,7 @@ static int gdb_handle_packet(GDBState *s
         type = strtoul(p, (char **)&p, 16);
         if (*p == ',')
             p++;
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, (char **)&p, 16);
Index: qemu-git-trunk/target-alpha/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-alpha/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-alpha/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -500,4 +500,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* !defined (__CPU_ALPHA_H__) */
Index: qemu-git-trunk/target-arm/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-arm/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-arm/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1539,4 +1539,7 @@ enum {
     QEMU_PSCI_CONDUIT_HVC = 2,
 };
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-cris/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-cris/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-cris/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -277,4 +277,7 @@ void cris_cpu_list(FILE *f, fprintf_func
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-i386/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-i386/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-i386/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1378,4 +1378,7 @@ void enable_compat_apic_id_mode(void);
 #define APIC_DEFAULT_ADDRESS 0xfee00000
 #define APIC_SPACE_SIZE      0x100000
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* CPU_I386_H */
Index: qemu-git-trunk/target-lm32/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-lm32/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-lm32/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -248,4 +248,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-m68k/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-m68k/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-m68k/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -254,4 +254,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-microblaze/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-microblaze/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-microblaze/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -364,4 +364,7 @@ void mb_cpu_unassigned_access(CPUState *
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-mips/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-mips/cpu.h	2014-12-05 18:40:55.358929758 +0000
+++ qemu-git-trunk/target-mips/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1008,4 +1008,38 @@ static inline void cpu_mips_store_cause(
 }
 #endif
 
+/* Macros below used by gdbstub.  */
+#define target_address(cs, addr) mips_address(&MIPS_CPU(cs)->env, (addr))
+
+/* System emulation always uses the processor's native register size;
+   any processor that supports at least MIPS III instructions has 64-bit
+   registers.  User emulation uses the ABI register size.  */
+#ifndef CONFIG_USER_ONLY
+# define mips64_p(env) (((env)->insn_flags & ISA_MIPS3) != 0)
+# define mips_address(env, addr)                                        \
+    (mips64_p(env) ? (addr) : ((int64_t)(int32_t)(addr)))
+# define mips_get_reg(env, buf, val)                                    \
+    (mips64_p(env) ? gdb_get_reg64((buf), (val)) : gdb_get_reg32((buf), (val)))
+# define mips_set_reg(env, buf)                                         \
+    (mips64_p(env) ? ldq_p(buf) : ((int64_t)(int32_t)ldl_p(buf)))
+# define mips_regsize(env) (4 << mips64_p(env))
+#elif defined(TARGET_ABI_MIPSN64)
+# define mips_address(env, addr) (addr)
+# define mips_get_reg(env, buf, val) gdb_get_reg64((buf), (val))
+# define mips_set_reg(env, buf) ldq_p(buf)
+# define mips_regsize(env) 8
+#elif defined(TARGET_ABI_MIPSN32)
+# define mips_address(env, addr) ((int64_t)(int32_t)(addr))
+# define mips_get_reg(env, buf, val) gdb_get_reg64((buf), (val))
+# define mips_set_reg(env, buf) ldq_p(buf)
+# define mips_regsize(env) 8
+#elif defined(TARGET_ABI_MIPSO32)
+# define mips_address(env, addr) ((int64_t)(int32_t)(addr))
+# define mips_get_reg(env, buf, val) gdb_get_reg32((buf), (val))
+# define mips_set_reg(env, buf) (((int64_t)(int32_t)ldl_p(buf)))
+# define mips_regsize(env) 4
+#else
+# error Unsupported user-mode MIPS ABI
+#endif
+
 #endif /* !defined (__MIPS_CPU_H__) */
Index: qemu-git-trunk/target-mips/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/target-mips/gdbstub.c	2014-12-05 18:40:52.857534413 +0000
+++ qemu-git-trunk/target-mips/gdbstub.c	2014-12-05 18:41:00.358928442 +0000
@@ -21,54 +21,56 @@
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
 
+#include "cpu.h"
+
 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
     CPUMIPSState *env = &cpu->env;
 
     if (n < 32) {
-        return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
+        return mips_get_reg(env, mem_buf, env->active_tc.gpr[n]);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
         switch (n) {
         case 70:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
+            return mips_get_reg(env, mem_buf, (int32_t)env->active_fpu.fcr31);
         case 71:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
+            return mips_get_reg(env, mem_buf, (int32_t)env->active_fpu.fcr0);
         default:
             if (env->CP0_Status & (1 << CP0St_FR)) {
-                return gdb_get_regl(mem_buf,
+                return mips_get_reg(env, mem_buf,
                     env->active_fpu.fpr[n - 38].d);
             } else {
-                return gdb_get_regl(mem_buf,
+                return mips_get_reg(env, mem_buf,
                     env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
             }
         }
     }
     switch (n) {
     case 32:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_Status);
     case 33:
-        return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
+        return mips_get_reg(env, mem_buf, env->active_tc.LO[0]);
     case 34:
-        return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
+        return mips_get_reg(env, mem_buf, env->active_tc.HI[0]);
     case 35:
-        return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
+        return mips_get_reg(env, mem_buf, env->CP0_BadVAddr);
     case 36:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_Cause);
     case 37:
-        return gdb_get_regl(mem_buf, env->active_tc.PC |
-                                     !!(env->hflags & MIPS_HFLAG_M16));
+        return mips_get_reg(env, mem_buf, env->active_tc.PC |
+                                          !!(env->hflags & MIPS_HFLAG_M16));
     case 72:
-        return gdb_get_regl(mem_buf, 0); /* fp */
+        return mips_get_reg(env, mem_buf, 0); /* fp */
     case 89:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_PRid);
     default:
         if (n > 89) {
             return 0;
         }
         /* 16 embedded regs.  */
-        return gdb_get_regl(mem_buf, 0);
+        return mips_get_reg(env, mem_buf, 0);
     }
 
     return 0;
@@ -80,11 +82,11 @@ int mips_cpu_gdb_write_register(CPUState
     CPUMIPSState *env = &cpu->env;
     target_ulong tmp;
 
-    tmp = ldtul_p(mem_buf);
+    tmp = mips_set_reg(env, mem_buf);
 
     if (n < 32) {
         env->active_tc.gpr[n] = tmp;
-        return sizeof(target_ulong);
+        return mips_regsize(env);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
         switch (n) {
@@ -106,7 +108,7 @@ int mips_cpu_gdb_write_register(CPUState
             }
             break;
         }
-        return sizeof(target_ulong);
+        return mips_regsize(env);
     }
     switch (n) {
     case 32:
@@ -146,5 +148,5 @@ int mips_cpu_gdb_write_register(CPUState
         break;
     }
 
-    return sizeof(target_ulong);
+    return mips_regsize(env);
 }
Index: qemu-git-trunk/target-moxie/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-moxie/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-moxie/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -155,4 +155,7 @@ static inline void cpu_get_tb_cpu_state(
 int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
                                int rw, int mmu_idx);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* _CPU_MOXIE_H */
Index: qemu-git-trunk/target-openrisc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-openrisc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-openrisc/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -427,4 +427,7 @@ static inline target_ulong cpu_get_pc(CP
     return env->pc;
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* CPU_OPENRISC_H */
Index: qemu-git-trunk/target-ppc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-ppc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-ppc/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -2310,4 +2310,7 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
  */
 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* !defined (__CPU_PPC_H__) */
Index: qemu-git-trunk/target-s390x/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-s390x/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-s390x/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -1149,4 +1149,7 @@ static inline int s390_assign_subch_ioev
     }
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-sh4/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-sh4/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-sh4/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -354,4 +354,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif				/* _CPU_SH4_H */
Index: qemu-git-trunk/target-sparc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-sparc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-sparc/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -753,4 +753,7 @@ static inline bool tb_am_enabled(int tb_
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-tricore/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-tricore/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-tricore/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -400,4 +400,7 @@ static inline void cpu_pc_from_tb(CPUTri
     env->PC = tb->pc;
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /*__TRICORE_CPU_H__ */
Index: qemu-git-trunk/target-unicore32/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-unicore32/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-unicore32/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -159,4 +159,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *
 void uc32_translate_init(void);
 void switch_mode(CPUUniCore32State *, int);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* QEMU_UNICORE32_CPU_H */
Index: qemu-git-trunk/target-xtensa/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-xtensa/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-xtensa/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -533,4 +533,7 @@ static inline void cpu_get_tb_cpu_state(
 #include "exec/cpu-all.h"
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Peter Maydell]

On 10 December 2014 at 18:53, Maciej W. Rozycki <macro@codesourcery.com> wrote:
> Mechanically add new n32/n64 configuration files copying the relevant
> preexisting ones, fixing the system emulation configuration build, that
> breaks due to the lack of the respective configuration files, for the
> `mipsn32' and `mipsn32el' targets on this occasion as well.
>
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
>  To be applied first so as not to break the build and consequently
> bisection with the configuration changes posted next.
>
>   Maciej
>
> qemu-mips-configs.diff
> Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
> Index: qemu-git-trunk/default-configs/mipsn32el-softmmu.mak
> Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
> Index: qemu-git-trunk/default-configs/mipsn64el-softmmu.mak

Some of these look weird. n32 and n64 are ABIs, right? We
shouldn't have extra -softmmu configs for different ABIs,
the guest can deal with those. The MIPS config name variants
that are only ABI related should only result in new -linux-user
binaries (where we need a binary per Linux syscall ABI).

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Maciej W. Rozycki]

On Wed, 10 Dec 2014, Peter Maydell wrote:

> > Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
> > Index: qemu-git-trunk/default-configs/mipsn32el-softmmu.mak
> > Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
> > Index: qemu-git-trunk/default-configs/mipsn64el-softmmu.mak
> 
> Some of these look weird. n32 and n64 are ABIs, right? We
> shouldn't have extra -softmmu configs for different ABIs,
> the guest can deal with those. The MIPS config name variants
> that are only ABI related should only result in new -linux-user
> binaries (where we need a binary per Linux syscall ABI).

 This is a tricky change, the system emulation mode configuration also has 
an ELF loader (invoked with the -kernel option) and as such is also 
affected.  There are three MIPS ELF flavours corresponding to the three 
ABIs: ELF32 no-ABI2 for o32, ELF32 ABI2 for n32 and ELF64 for n64 (ABI2 is 
an ELF file header flag).  The two ELF32 flavours are I think close enough 
to each other as far as executables (as opposed to intermediate objects) 
are concerned that a single QEMU binary might be able to handle them as it 
stands.  Of course ELF32 ABI2 is incompatible to any 32-bit processors and 
such executables must be rejected when emulating a 32-bit processor.

 So with my proposal and -softmmu configs:

- mipsn64|mipsn64el -- handle ELF64 (n64) binaries with only 64-bit 
                       processors available for emulation, 

- mipsn32|mipsn32el -- handle ELF32 (n32) binaries with only 64-bit 
                       processors available for emulation,

- mips64|mips64el   -- handle ELF32 (o32, maybe n32) binaries with both 
                       32-bit and 64-bit processors available for 
                       emulation,

- mips|mipsel       -- handle ELF32 (o32) binaries with only 32-bit 
                       processors available for emulation (configuration 
                       optimised for 32-bit hosts).

Each of them will be suitable for running different bare-metal 
applications.  As I say, we may be able to come up with better target 
names, I am open to proposals.

 As noted in 0/3 ideally we'd handle all ELF flavours with a single 
binary.  Then we could have two system configurations only, mips|mipsel (a 
limited configuration for 32-bit host optimisation) and mips64|mips64el (a 
full configuration).  That could apply to both the system and the user 
emulation mode, although the effort required to handle the former is a 
subset of that for the latter, and also looks quite substantially smaller 
to me.  The changes I propose here do not preclude it from happening in 
the future, they are merely intended to bring some order to what we have 
now.

 Does this explanation makes things addressed here a bit clearer to you?

  Maciej

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Peter Maydell]

On 10 December 2014 at 20:29, Maciej W. Rozycki <macro@codesourcery.com> wrote:
> On Wed, 10 Dec 2014, Peter Maydell wrote:
>
>> > Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
>> > Index: qemu-git-trunk/default-configs/mipsn32el-softmmu.mak
>> > Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
>> > Index: qemu-git-trunk/default-configs/mipsn64el-softmmu.mak
>>
>> Some of these look weird. n32 and n64 are ABIs, right? We
>> shouldn't have extra -softmmu configs for different ABIs,
>> the guest can deal with those. The MIPS config name variants
>> that are only ABI related should only result in new -linux-user
>> binaries (where we need a binary per Linux syscall ABI).
>
>  This is a tricky change, the system emulation mode configuration also has
> an ELF loader (invoked with the -kernel option) and as such is also
> affected.  There are three MIPS ELF flavours corresponding to the three
> ABIs: ELF32 no-ABI2 for o32, ELF32 ABI2 for n32 and ELF64 for n64 (ABI2 is
> an ELF file header flag).  The two ELF32 flavours are I think close enough
> to each other as far as executables (as opposed to intermediate objects)
> are concerned that a single QEMU binary might be able to handle them as it
> stands.  Of course ELF32 ABI2 is incompatible to any 32-bit processors and
> such executables must be rejected when emulating a 32-bit processor.

So this is only an issue because of the bare-metal ELF loading?
We should make that handle the various bare metal EXEs correctly
for the CPUs that each softmmu config currently supports.

>  As noted in 0/3 ideally we'd handle all ELF flavours with a single
> binary.  Then we could have two system configurations only, mips|mipsel (a
> limited configuration for 32-bit host optimisation) and mips64|mips64el (a
> full configuration).

I think this is the right way to go.

>  That could apply to both the system and the user
> emulation mode, although the effort required to handle the former is a
> subset of that for the latter, and also looks quite substantially smaller
> to me.

User emulation is a harder problem, because we compile-time code in
things like structure layouts and data type sizes. That's why we have
one binary per ABI. System emulation really should not care about
this anywhere near as much.

> The changes I propose here do not preclude it from happening in
> the future, they are merely intended to bring some order to what we have
> now.

The problem is that adding new QEMU executables is effectively
extending our user-facing interface. We really shouldn't do that
in the wrong way if we can avoid it (it's hard to undo later
without breaking peoples' setups).

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Maciej W. Rozycki]

On Wed, 10 Dec 2014, Peter Maydell wrote:

> >  This is a tricky change, the system emulation mode configuration also has
> > an ELF loader (invoked with the -kernel option) and as such is also
> > affected.  There are three MIPS ELF flavours corresponding to the three
> > ABIs: ELF32 no-ABI2 for o32, ELF32 ABI2 for n32 and ELF64 for n64 (ABI2 is
> > an ELF file header flag).  The two ELF32 flavours are I think close enough
> > to each other as far as executables (as opposed to intermediate objects)
> > are concerned that a single QEMU binary might be able to handle them as it
> > stands.  Of course ELF32 ABI2 is incompatible to any 32-bit processors and
> > such executables must be rejected when emulating a 32-bit processor.
> 
> So this is only an issue because of the bare-metal ELF loading?
> We should make that handle the various bare metal EXEs correctly
> for the CPUs that each softmmu config currently supports.
> 
> >  As noted in 0/3 ideally we'd handle all ELF flavours with a single
> > binary.  Then we could have two system configurations only, mips|mipsel (a
> > limited configuration for 32-bit host optimisation) and mips64|mips64el (a
> > full configuration).
> 
> I think this is the right way to go.

 Except that apart from coming to an agreement someone has to make it 
happen yet. ;)

> >  That could apply to both the system and the user
> > emulation mode, although the effort required to handle the former is a
> > subset of that for the latter, and also looks quite substantially smaller
> > to me.
> 
> User emulation is a harder problem, because we compile-time code in
> things like structure layouts and data type sizes. That's why we have
> one binary per ABI. System emulation really should not care about
> this anywhere near as much.

 We still need to come up with sensible target names and clean up the 
current situation.  What I think is particularly important about this 
series is 3/3.  And 2/3 defines a consistent set of macros to drive 3/3.

> > The changes I propose here do not preclude it from happening in
> > the future, they are merely intended to bring some order to what we have
> > now.
> 
> The problem is that adding new QEMU executables is effectively
> extending our user-facing interface. We really shouldn't do that
> in the wrong way if we can avoid it (it's hard to undo later
> without breaking peoples' setups).

 Fair enough, I want to move forward though.  Would it make you happy if I 
dropped the new -softmmu configs and made mipsn32|mipsn32el and 
mipsn64|mipsn64el only accept -user configs instead (failing gracefully 
rather than abruptly as mipsn32|mipsn32el do now)?

  Maciej

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Peter Maydell]

On 10 December 2014 at 22:14, Maciej W. Rozycki <macro@codesourcery.com> wrote:
> On Wed, 10 Dec 2014, Peter Maydell wrote:

>> >  As noted in 0/3 ideally we'd handle all ELF flavours with a single
>> > binary.  Then we could have two system configurations only, mips|mipsel (a
>> > limited configuration for 32-bit host optimisation) and mips64|mips64el (a
>> > full configuration).
>>
>> I think this is the right way to go.
>
>  Except that apart from coming to an agreement someone has to make it
> happen yet. ;)

Ah, but I'm happy with the current state of the codebase...

>> > The changes I propose here do not preclude it from happening in
>> > the future, they are merely intended to bring some order to what we have
>> > now.
>>
>> The problem is that adding new QEMU executables is effectively
>> extending our user-facing interface. We really shouldn't do that
>> in the wrong way if we can avoid it (it's hard to undo later
>> without breaking peoples' setups).
>
>  Fair enough, I want to move forward though.  Would it make you happy if I
> dropped the new -softmmu configs and made mipsn32|mipsn32el and
> mipsn64|mipsn64el only accept -user configs instead (failing gracefully
> rather than abruptly as mipsn32|mipsn32el do now)?

Er, I'm not sure what you mean there. Trying a softmmu config for
mipsn32 or mipsn32el fails gracefully already:

manooth$ (cd build/mips && ../../configure --target-list=mipsn32-softmmu)

ERROR: Unknown target name 'mipsn32-softmmu'

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Maciej W. Rozycki]

On Wed, 10 Dec 2014, Peter Maydell wrote:

> >  Except that apart from coming to an agreement someone has to make it
> > happen yet. ;)
> 
> Ah, but I'm happy with the current state of the codebase...

 Ack.

> >  Fair enough, I want to move forward though.  Would it make you happy if I
> > dropped the new -softmmu configs and made mipsn32|mipsn32el and
> > mipsn64|mipsn64el only accept -user configs instead (failing gracefully
> > rather than abruptly as mipsn32|mipsn32el do now)?
> 
> Er, I'm not sure what you mean there. Trying a softmmu config for
> mipsn32 or mipsn32el fails gracefully already:
> 
> manooth$ (cd build/mips && ../../configure --target-list=mipsn32-softmmu)
> 
> ERROR: Unknown target name 'mipsn32-softmmu'

 It looks like the issue I had in mind has been fixed in a generic way 
then since I last checked.  Previously a build error happened sometime 
along the process.  Apologies for not double-checking with current trunk.  
I'll send updates.

  Maciej

[Qemu-devel] [PATCH v2 1/2] target-mips: Rework ABIs to allow all required configurations

[Maciej W. Rozycki]

Rework the MIPS ABIs and CPU emulations available according to the 
following target list:

- mips|mipsel       -- 32-bit CPUs only, system and user emulation mode, 
                       o32 user ABI,

- mips64|mips64el   -- 32-bit and 64-bit CPUs, system and user emulation 
                       mode, o32 user ABI,

- mipsn32|mipsn32el -- 64-bit CPUs only, user emulation mode only, n32 
                       user ABI,

- mipsn64|mipsn64el -- 64-bit CPUs only, user emulation mode only, n64 
                       user ABI.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
Changes from v1:

- remove n32 and n64 system emulation mode configurations,

- fold 1/3 and 2/3 into 1/2.

qemu-mips64-abis.diff
Index: qemu-git-trunk/bsd-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/bsd-user/elfload.c	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/bsd-user/elfload.c	2014-12-11 00:05:37.878938825 +0000
@@ -381,7 +381,7 @@ static inline void init_thread(struct ta
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
Index: qemu-git-trunk/configure
===================================================================
--- qemu-git-trunk.orig/configure	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/configure	2014-12-11 00:05:37.878938825 +0000
@@ -4982,7 +4982,7 @@ target_name=`echo $target | cut -d '-' -
 target_bigendian="no"
 
 case "$target_name" in
-  armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  armeb|lm32|m68k|microblaze|mips|mips64|mipsn32|mipsn64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
@@ -5057,17 +5057,28 @@ case "$target_name" in
   ;;
   mips|mipsel)
     TARGET_ARCH=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
     echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
   ;;
+  mips64|mips64el)
+    TARGET_ARCH=mips64
+    TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
+    echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
+    echo "TARGET_ABI32=y" >> $config_target_mak
+  ;;
   mipsn32|mipsn32el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak
     echo "TARGET_ABI32=y" >> $config_target_mak
   ;;
-  mips64|mips64el)
+  mipsn64|mipsn64el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
   ;;
   tricore)
Index: qemu-git-trunk/default-configs/mipsn64-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64-linux-user.mak	2014-12-11 00:05:45.378923933 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64-linux-user
Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64el-linux-user.mak	2014-12-11 00:05:45.378923933 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64el-linux-user
Index: qemu-git-trunk/include/exec/poison.h
===================================================================
--- qemu-git-trunk.orig/include/exec/poison.h	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/include/exec/poison.h	2014-12-11 00:05:37.878938825 +0000
@@ -13,7 +13,11 @@
 #pragma GCC poison TARGET_LM32
 #pragma GCC poison TARGET_M68K
 #pragma GCC poison TARGET_MIPS
+#pragma GCC poison TARGET_MIPS32
 #pragma GCC poison TARGET_MIPS64
+#pragma GCC poison TARGET_ABI_MIPSO32
+#pragma GCC poison TARGET_ABI_MIPSN32
+#pragma GCC poison TARGET_ABI_MIPSN64
 #pragma GCC poison TARGET_OPENRISC
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPCEMB
Index: qemu-git-trunk/linux-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/linux-user/elfload.c	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/linux-user/elfload.c	2014-12-11 00:05:37.878938825 +0000
@@ -875,7 +875,7 @@ static void elf_core_copy_regs(target_el
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
@@ -896,10 +896,10 @@ typedef target_elf_greg_t target_elf_gre
 
 /* See linux kernel: arch/mips/include/asm/reg.h.  */
 enum {
-#ifdef TARGET_MIPS64
-    TARGET_EF_R0 = 0,
-#else
+#ifdef TARGET_ABI_MIPSO32
     TARGET_EF_R0 = 6,
+#else
+    TARGET_EF_R0 = 0,
 #endif
     TARGET_EF_R26 = TARGET_EF_R0 + 26,
     TARGET_EF_R27 = TARGET_EF_R0 + 27,
Index: qemu-git-trunk/linux-user/main.c
===================================================================
--- qemu-git-trunk.orig/linux-user/main.c	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/linux-user/main.c	2014-12-11 00:05:37.878938825 +0000
@@ -3928,7 +3928,7 @@ int main(int argc, char **argv, char **e
         cpu_model = "Fujitsu MB86904";
 #endif
 #elif defined(TARGET_MIPS)
-#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+#ifdef TARGET_MIPS64
         cpu_model = "5KEf";
 #else
         cpu_model = "24Kf";
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c	2014-12-11 00:05:18.000000000 +0000
+++ qemu-git-trunk/target-mips/translate_init.c	2014-12-11 00:05:37.878938825 +0000
@@ -107,6 +107,7 @@ struct mips_def_t {
 /* MIPS CPU definitions */
 static const mips_def_t mips_defs[] =
 {
+#if defined(TARGET_MIPS32)
     {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
@@ -421,6 +422,7 @@ static const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
         .mmu_type = MMU_TYPE_R4000,
     },
+#endif
 #if defined(TARGET_MIPS64)
     {
         .name = "R4000",

[Qemu-devel] [PATCH v2 2/2] target-mips: Set GDB register widths correctly

[Maciej W. Rozycki]

Set register widths in the GDB stub as follows:

- for the system emulation mode -- to the native register size of the 
  processor selected, any MIPS I, MIPS II or MIPS32 (any revision) 
  processor will have 32-bit general purpose registers and any MIPS III, 
  MIPS IV or MIPS64 (again, any revision) will have 64-bit general 
  purpose registers,

- for the user emulation mode -- to the register size defined by the 
  ABI, that is the emulation of the o32 ABI will have 32-bit general 
  purpose registers and the emulation of the n32 and n64 ABIs will have 
  64-bit general purpose registers.

With the the user emulation mode, the o32 ABI and a 64-bit processor 
selected handle native 64-bit registers such that on reads they are 
truncated to low 32 bits only and on writes the 32-bit value stored is 
sign-extended from bit #31, which is how hardware instructions supported 
with the o32 ABI have been defined in the architecture.

Also correctly wrap the address space in the 32-bit o32 and n32 ABIs by 
sign-extending any addresses processed from bit #31, matching how the 
hardware operates in the user mode according to CP0.Status.UX == 0 and 
CP0.Status.PX == 0 (for o32) and CP0.Status.UX == 0 and CP0.Status.PX == 
1 (for n32).  This is also how GDB works operating on real processors in 
conjunction with JTAG hardware and associated debug-mode firmware across 
all execution modes.

As a side effect fix the case where registers are presented as 64-bit 
quantities while talking to a 32-bit processor.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
Changes from v1:

- rename 3/3 to 2/2.

qemu-mips-regsize.diff
Index: qemu-git-trunk/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/gdbstub.c	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/gdbstub.c	2014-12-05 18:41:00.358928442 +0000
@@ -789,7 +789,7 @@ static int gdb_handle_packet(GDBState *s
         break;
     case 'c':
         if (*p != '\0') {
-            addr = strtoull(p, (char **)&p, 16);
+            addr = target_address(s->c_cpu, strtoull(p, (char **)&p, 16));
             gdb_set_cpu_pc(s, addr);
         }
         s->signal = 0;
@@ -875,7 +875,7 @@ static int gdb_handle_packet(GDBState *s
         break;
     case 's':
         if (*p != '\0') {
-            addr = strtoull(p, (char **)&p, 16);
+            addr = target_address(s->c_cpu, strtoull(p, (char **)&p, 16));
             gdb_set_cpu_pc(s, addr);
         }
         cpu_single_step(s->c_cpu, sstep_flags);
@@ -930,7 +930,7 @@ static int gdb_handle_packet(GDBState *s
         put_packet(s, "OK");
         break;
     case 'm':
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, NULL, 16);
@@ -942,7 +942,7 @@ static int gdb_handle_packet(GDBState *s
         }
         break;
     case 'M':
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, (char **)&p, 16);
@@ -987,7 +987,7 @@ static int gdb_handle_packet(GDBState *s
         type = strtoul(p, (char **)&p, 16);
         if (*p == ',')
             p++;
-        addr = strtoull(p, (char **)&p, 16);
+        addr = target_address(s->g_cpu, strtoull(p, (char **)&p, 16));
         if (*p == ',')
             p++;
         len = strtoull(p, (char **)&p, 16);
Index: qemu-git-trunk/target-alpha/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-alpha/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-alpha/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -500,4 +500,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* !defined (__CPU_ALPHA_H__) */
Index: qemu-git-trunk/target-arm/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-arm/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-arm/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1539,4 +1539,7 @@ enum {
     QEMU_PSCI_CONDUIT_HVC = 2,
 };
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-cris/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-cris/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-cris/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -277,4 +277,7 @@ void cris_cpu_list(FILE *f, fprintf_func
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-i386/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-i386/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-i386/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1378,4 +1378,7 @@ void enable_compat_apic_id_mode(void);
 #define APIC_DEFAULT_ADDRESS 0xfee00000
 #define APIC_SPACE_SIZE      0x100000
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* CPU_I386_H */
Index: qemu-git-trunk/target-lm32/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-lm32/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-lm32/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -248,4 +248,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-m68k/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-m68k/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-m68k/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -254,4 +254,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-microblaze/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-microblaze/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-microblaze/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -364,4 +364,7 @@ void mb_cpu_unassigned_access(CPUState *
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-mips/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-mips/cpu.h	2014-12-05 18:40:55.358929758 +0000
+++ qemu-git-trunk/target-mips/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -1008,4 +1008,38 @@ static inline void cpu_mips_store_cause(
 }
 #endif
 
+/* Macros below used by gdbstub.  */
+#define target_address(cs, addr) mips_address(&MIPS_CPU(cs)->env, (addr))
+
+/* System emulation always uses the processor's native register size;
+   any processor that supports at least MIPS III instructions has 64-bit
+   registers.  User emulation uses the ABI register size.  */
+#ifndef CONFIG_USER_ONLY
+# define mips64_p(env) (((env)->insn_flags & ISA_MIPS3) != 0)
+# define mips_address(env, addr)                                        \
+    (mips64_p(env) ? (addr) : ((int64_t)(int32_t)(addr)))
+# define mips_get_reg(env, buf, val)                                    \
+    (mips64_p(env) ? gdb_get_reg64((buf), (val)) : gdb_get_reg32((buf), (val)))
+# define mips_set_reg(env, buf)                                         \
+    (mips64_p(env) ? ldq_p(buf) : ((int64_t)(int32_t)ldl_p(buf)))
+# define mips_regsize(env) (4 << mips64_p(env))
+#elif defined(TARGET_ABI_MIPSN64)
+# define mips_address(env, addr) (addr)
+# define mips_get_reg(env, buf, val) gdb_get_reg64((buf), (val))
+# define mips_set_reg(env, buf) ldq_p(buf)
+# define mips_regsize(env) 8
+#elif defined(TARGET_ABI_MIPSN32)
+# define mips_address(env, addr) ((int64_t)(int32_t)(addr))
+# define mips_get_reg(env, buf, val) gdb_get_reg64((buf), (val))
+# define mips_set_reg(env, buf) ldq_p(buf)
+# define mips_regsize(env) 8
+#elif defined(TARGET_ABI_MIPSO32)
+# define mips_address(env, addr) ((int64_t)(int32_t)(addr))
+# define mips_get_reg(env, buf, val) gdb_get_reg32((buf), (val))
+# define mips_set_reg(env, buf) (((int64_t)(int32_t)ldl_p(buf)))
+# define mips_regsize(env) 4
+#else
+# error Unsupported user-mode MIPS ABI
+#endif
+
 #endif /* !defined (__MIPS_CPU_H__) */
Index: qemu-git-trunk/target-mips/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/target-mips/gdbstub.c	2014-12-05 18:40:52.857534413 +0000
+++ qemu-git-trunk/target-mips/gdbstub.c	2014-12-05 18:41:00.358928442 +0000
@@ -21,54 +21,56 @@
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
 
+#include "cpu.h"
+
 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
     CPUMIPSState *env = &cpu->env;
 
     if (n < 32) {
-        return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
+        return mips_get_reg(env, mem_buf, env->active_tc.gpr[n]);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
         switch (n) {
         case 70:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
+            return mips_get_reg(env, mem_buf, (int32_t)env->active_fpu.fcr31);
         case 71:
-            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
+            return mips_get_reg(env, mem_buf, (int32_t)env->active_fpu.fcr0);
         default:
             if (env->CP0_Status & (1 << CP0St_FR)) {
-                return gdb_get_regl(mem_buf,
+                return mips_get_reg(env, mem_buf,
                     env->active_fpu.fpr[n - 38].d);
             } else {
-                return gdb_get_regl(mem_buf,
+                return mips_get_reg(env, mem_buf,
                     env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
             }
         }
     }
     switch (n) {
     case 32:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_Status);
     case 33:
-        return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
+        return mips_get_reg(env, mem_buf, env->active_tc.LO[0]);
     case 34:
-        return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
+        return mips_get_reg(env, mem_buf, env->active_tc.HI[0]);
     case 35:
-        return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
+        return mips_get_reg(env, mem_buf, env->CP0_BadVAddr);
     case 36:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_Cause);
     case 37:
-        return gdb_get_regl(mem_buf, env->active_tc.PC |
-                                     !!(env->hflags & MIPS_HFLAG_M16));
+        return mips_get_reg(env, mem_buf, env->active_tc.PC |
+                                          !!(env->hflags & MIPS_HFLAG_M16));
     case 72:
-        return gdb_get_regl(mem_buf, 0); /* fp */
+        return mips_get_reg(env, mem_buf, 0); /* fp */
     case 89:
-        return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
+        return mips_get_reg(env, mem_buf, (int32_t)env->CP0_PRid);
     default:
         if (n > 89) {
             return 0;
         }
         /* 16 embedded regs.  */
-        return gdb_get_regl(mem_buf, 0);
+        return mips_get_reg(env, mem_buf, 0);
     }
 
     return 0;
@@ -80,11 +82,11 @@ int mips_cpu_gdb_write_register(CPUState
     CPUMIPSState *env = &cpu->env;
     target_ulong tmp;
 
-    tmp = ldtul_p(mem_buf);
+    tmp = mips_set_reg(env, mem_buf);
 
     if (n < 32) {
         env->active_tc.gpr[n] = tmp;
-        return sizeof(target_ulong);
+        return mips_regsize(env);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
         switch (n) {
@@ -106,7 +108,7 @@ int mips_cpu_gdb_write_register(CPUState
             }
             break;
         }
-        return sizeof(target_ulong);
+        return mips_regsize(env);
     }
     switch (n) {
     case 32:
@@ -146,5 +148,5 @@ int mips_cpu_gdb_write_register(CPUState
         break;
     }
 
-    return sizeof(target_ulong);
+    return mips_regsize(env);
 }
Index: qemu-git-trunk/target-moxie/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-moxie/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-moxie/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -155,4 +155,7 @@ static inline void cpu_get_tb_cpu_state(
 int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
                                int rw, int mmu_idx);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* _CPU_MOXIE_H */
Index: qemu-git-trunk/target-openrisc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-openrisc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-openrisc/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -427,4 +427,7 @@ static inline target_ulong cpu_get_pc(CP
     return env->pc;
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* CPU_OPENRISC_H */
Index: qemu-git-trunk/target-ppc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-ppc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-ppc/cpu.h	2014-12-05 18:41:00.358928442 +0000
@@ -2310,4 +2310,7 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
  */
 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* !defined (__CPU_PPC_H__) */
Index: qemu-git-trunk/target-s390x/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-s390x/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-s390x/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -1149,4 +1149,7 @@ static inline int s390_assign_subch_ioev
     }
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-sh4/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-sh4/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-sh4/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -354,4 +354,7 @@ static inline void cpu_get_tb_cpu_state(
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif				/* _CPU_SH4_H */
Index: qemu-git-trunk/target-sparc/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-sparc/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-sparc/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -753,4 +753,7 @@ static inline bool tb_am_enabled(int tb_
 
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif
Index: qemu-git-trunk/target-tricore/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-tricore/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-tricore/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -400,4 +400,7 @@ static inline void cpu_pc_from_tb(CPUTri
     env->PC = tb->pc;
 }
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /*__TRICORE_CPU_H__ */
Index: qemu-git-trunk/target-unicore32/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-unicore32/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-unicore32/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -159,4 +159,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *
 void uc32_translate_init(void);
 void switch_mode(CPUUniCore32State *, int);
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif /* QEMU_UNICORE32_CPU_H */
Index: qemu-git-trunk/target-xtensa/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-xtensa/cpu.h	2014-12-05 18:38:40.847529339 +0000
+++ qemu-git-trunk/target-xtensa/cpu.h	2014-12-05 18:41:00.858923584 +0000
@@ -533,4 +533,7 @@ static inline void cpu_get_tb_cpu_state(
 #include "exec/cpu-all.h"
 #include "exec/exec-all.h"
 
+/* Used by gdbstub.  */
+#define target_address(cs, addr) (addr)
+
 #endif

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Peter Maydell]

On 10 December 2014 at 23:25, Maciej W. Rozycki <macro@codesourcery.com> wrote:
> On Wed, 10 Dec 2014, Peter Maydell wrote:
>
>> >  Except that apart from coming to an agreement someone has to make it
>> > happen yet. ;)
>>
>> Ah, but I'm happy with the current state of the codebase...
>
>  Ack.

To clarify, that was a slightly tongue-in-cheek response, but I
do actually feel strongly enough that we shouldn't create new
wrong executables that I'd rather we left the bugs here unaddressed
than try to fix them with a lot of new softmmu executables.

>> Er, I'm not sure what you mean there. Trying a softmmu config for
>> mipsn32 or mipsn32el fails gracefully already:
>>
>> manooth$ (cd build/mips && ../../configure --target-list=mipsn32-softmmu)
>>
>> ERROR: Unknown target name 'mipsn32-softmmu'
>
>  It looks like the issue I had in mind has been fixed in a generic way
> then since I last checked.  Previously a build error happened sometime
> along the process.  Apologies for not double-checking with current trunk.
> I'll send updates.

Yes, we fixed configure to sanity check user target-list arguments
some time last year. Note that the list of valid targets is driven
by looking at what files exist in default-configs/, so you'll want
to delete any stale or local files you have there from previous
versions of this patchset.

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/3] target-mips: Add n32/n64 configuration files

[Maciej W. Rozycki]

On Thu, 11 Dec 2014, Peter Maydell wrote:

> >> >  Except that apart from coming to an agreement someone has to make it
> >> > happen yet. ;)
> >>
> >> Ah, but I'm happy with the current state of the codebase...
> >
> >  Ack.
> 
> To clarify, that was a slightly tongue-in-cheek response, but I
> do actually feel strongly enough that we shouldn't create new
> wrong executables that I'd rather we left the bugs here unaddressed
> than try to fix them with a lot of new softmmu executables.

 Sure, I have to clear the confusion I created here though.

 I have realised I ran all the earlier system emulation mode Linux testing 
with both o32 (ELF32) and n64 (ELF64) kernel images and just a single pair 
of QEMU executables for different endiannesses each.  So the ELF loader 
already supports all ELF executables.  So it's only the GDB stub's 
register width that has issues, as addressed here.

 Apologies for the wrong statements then, I misremembered things.

> >> Er, I'm not sure what you mean there. Trying a softmmu config for
> >> mipsn32 or mipsn32el fails gracefully already:
> >>
> >> manooth$ (cd build/mips && ../../configure --target-list=mipsn32-softmmu)
> >>
> >> ERROR: Unknown target name 'mipsn32-softmmu'
> >
> >  It looks like the issue I had in mind has been fixed in a generic way
> > then since I last checked.  Previously a build error happened sometime
> > along the process.  Apologies for not double-checking with current trunk.
> > I'll send updates.
> 
> Yes, we fixed configure to sanity check user target-list arguments
> some time last year. Note that the list of valid targets is driven
> by looking at what files exist in default-configs/, so you'll want
> to delete any stale or local files you have there from previous
> versions of this patchset.

 That's what I figured out before sending v2.  It looks to me like the 
cleanest way to handle it, you don't duplicate validity information in 
`configure'.

 Thanks for your review and hints, much appreciated.

  Maciej

[Qemu-devel] [PATCH v3 1/2] target-mips: Rework ABIs to allow all required configurations

[Maciej W. Rozycki]

Rework the MIPS ABIs and CPU emulations available according to the 
following target list:

- mips|mipsel       -- 32-bit CPUs only, system and user emulation mode, 
                       o32 user ABI,

- mips64|mips64el   -- 32-bit and 64-bit CPUs, system and user emulation 
                       mode, o32 user ABI,

- mipsn32|mipsn32el -- 64-bit CPUs only, user emulation mode only, n32 
                       user ABI,

- mipsn64|mipsn64el -- 64-bit CPUs only, user emulation mode only, n64 
                       user ABI.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
Changes from v1:

- remove n32 and n64 system emulation mode configurations,

- fold 1/3 and 2/3 into 1/2.

Changes from v2:

- only set the CP0.Status.FR bit for 64-bit ABIs rather than all 64-bit 
  configurations (translate.c).

 Strictly speaking the mask check should be an assertion failure or 
suchlike, because all 64-bit processors must support having this bit set 
to 1.  This will also require further updates for the FRXX ABI (where 
the bit indeed has to be set to 1 where possible) and R6 processors 
(where the bit is hardwired to 1 and will therefore fail the mask 
check).

 For the time being, the change is a move in the right direction, o32 
user mode emulation must not set this bit merely because it is writable.  
I'll check yet how this bug (that I missed) affected IEEE 754-2008 NaN 
testing, but I will only have results on Monday at the earliest.

  Maciej

qemu-mips64-abis.diff
Index: qemu-git-trunk/bsd-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/bsd-user/elfload.c	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/bsd-user/elfload.c	2014-12-12 18:05:29.138927913 +0000
@@ -381,7 +381,7 @@ static inline void init_thread(struct ta
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
Index: qemu-git-trunk/configure
===================================================================
--- qemu-git-trunk.orig/configure	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/configure	2014-12-12 18:05:29.138927913 +0000
@@ -4982,7 +4982,7 @@ target_name=`echo $target | cut -d '-' -
 target_bigendian="no"
 
 case "$target_name" in
-  armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  armeb|lm32|m68k|microblaze|mips|mips64|mipsn32|mipsn64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
@@ -5057,17 +5057,28 @@ case "$target_name" in
   ;;
   mips|mipsel)
     TARGET_ARCH=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
     echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
   ;;
+  mips64|mips64el)
+    TARGET_ARCH=mips64
+    TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips
+    echo "TARGET_MIPS32=y" >> $config_target_mak
+    echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
+    echo "TARGET_ABI32=y" >> $config_target_mak
+  ;;
   mipsn32|mipsn32el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak
     echo "TARGET_ABI32=y" >> $config_target_mak
   ;;
-  mips64|mips64el)
+  mipsn64|mipsn64el)
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
+    TARGET_ABI_DIR=mips64
     echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
   ;;
   tricore)
Index: qemu-git-trunk/default-configs/mipsn64-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64-linux-user.mak	2014-12-12 18:05:29.138927913 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64-linux-user
Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ qemu-git-trunk/default-configs/mipsn64el-linux-user.mak	2014-12-12 18:05:29.138927913 +0000
@@ -0,0 +1 @@
+# Default configuration for mipsn64el-linux-user
Index: qemu-git-trunk/include/exec/poison.h
===================================================================
--- qemu-git-trunk.orig/include/exec/poison.h	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/include/exec/poison.h	2014-12-12 18:05:29.138927913 +0000
@@ -13,7 +13,11 @@
 #pragma GCC poison TARGET_LM32
 #pragma GCC poison TARGET_M68K
 #pragma GCC poison TARGET_MIPS
+#pragma GCC poison TARGET_MIPS32
 #pragma GCC poison TARGET_MIPS64
+#pragma GCC poison TARGET_ABI_MIPSO32
+#pragma GCC poison TARGET_ABI_MIPSN32
+#pragma GCC poison TARGET_ABI_MIPSN64
 #pragma GCC poison TARGET_OPENRISC
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPCEMB
Index: qemu-git-trunk/linux-user/elfload.c
===================================================================
--- qemu-git-trunk.orig/linux-user/elfload.c	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/linux-user/elfload.c	2014-12-12 18:05:29.138927913 +0000
@@ -875,7 +875,7 @@ static void elf_core_copy_regs(target_el
 
 #define elf_check_arch(x) ( (x) == EM_MIPS )
 
-#ifdef TARGET_MIPS64
+#ifdef TARGET_ABI_MIPSN64
 #define ELF_CLASS   ELFCLASS64
 #else
 #define ELF_CLASS   ELFCLASS32
@@ -896,10 +896,10 @@ typedef target_elf_greg_t target_elf_gre
 
 /* See linux kernel: arch/mips/include/asm/reg.h.  */
 enum {
-#ifdef TARGET_MIPS64
-    TARGET_EF_R0 = 0,
-#else
+#ifdef TARGET_ABI_MIPSO32
     TARGET_EF_R0 = 6,
+#else
+    TARGET_EF_R0 = 0,
 #endif
     TARGET_EF_R26 = TARGET_EF_R0 + 26,
     TARGET_EF_R27 = TARGET_EF_R0 + 27,
Index: qemu-git-trunk/linux-user/main.c
===================================================================
--- qemu-git-trunk.orig/linux-user/main.c	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/linux-user/main.c	2014-12-12 18:05:29.138927913 +0000
@@ -3928,7 +3928,7 @@ int main(int argc, char **argv, char **e
         cpu_model = "Fujitsu MB86904";
 #endif
 #elif defined(TARGET_MIPS)
-#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+#ifdef TARGET_MIPS64
         cpu_model = "5KEf";
 #else
         cpu_model = "24Kf";
Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c	2014-12-12 18:05:26.000000000 +0000
+++ qemu-git-trunk/target-mips/translate.c	2014-12-12 18:05:52.148080884 +0000
@@ -19533,8 +19533,9 @@ void cpu_state_reset(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
         env->CP0_Status |= (1 << CP0St_MX);
     }
-# if defined(TARGET_MIPS64)
-    /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
+# if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+    /* For 64-bit ABIs, init the FR bit to 1 if the FPU unit is there
+       and the bit is writable.  */
     if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
         (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
         env->CP0_Status |= (1 << CP0St_FR);
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c	2014-12-12 18:05:17.000000000 +0000
+++ qemu-git-trunk/target-mips/translate_init.c	2014-12-12 18:05:29.138927913 +0000
@@ -107,6 +107,7 @@ struct mips_def_t {
 /* MIPS CPU definitions */
 static const mips_def_t mips_defs[] =
 {
+#if defined(TARGET_MIPS32)
     {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
@@ -421,6 +422,7 @@ static const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
         .mmu_type = MMU_TYPE_R4000,
     },
+#endif
 #if defined(TARGET_MIPS64)
     {
         .name = "R4000",

Re: [Qemu-devel] [PATCH v2 1/2] target-mips: Rework ABIs to allow all required configurations

[Leon Alrae]

On 11/12/2014 00:21, Maciej W. Rozycki wrote:
> Rework the MIPS ABIs and CPU emulations available according to the 
> following target list:
> 
> - mips|mipsel       -- 32-bit CPUs only, system and user emulation mode, 
>                        o32 user ABI,
> 
> - mips64|mips64el   -- 32-bit and 64-bit CPUs, system and user emulation 
>                        mode, o32 user ABI,

I'm not sure if it's a good idea to change the meaning of linux-user
qemu-mips64 and qemu-mips64el, this will cause unnecessary confusion in
my opinion. I think we’d be better off leaving it consistent across QEMU
versions.

Do we really need MIPS64 executables for o32 ABI for linux-user? They
would merely enable MIPS64 CPUs to run o32 programs. So far we've been
handling this by using 32-bit CPUs (artificial if the real CPU don't
exist), therefore I don't see an issue here. Also I'm concerned that
once we add new executables, it will be difficult to revert that change
later, thus we must be certain that this is the right way to go.

In general I would prefer to avoid changing the user interface and pain
related to breaking people's scripts whenever it's possible.

Regards,
Leon

Re: [Qemu-devel] [PATCH v2 1/2] target-mips: Rework ABIs to allow all required configurations

[Maciej W. Rozycki]

On Mon, 9 Feb 2015, Leon Alrae wrote:

> > Rework the MIPS ABIs and CPU emulations available according to the 
> > following target list:
> > 
> > - mips|mipsel       -- 32-bit CPUs only, system and user emulation mode, 
> >                        o32 user ABI,
> > 
> > - mips64|mips64el   -- 32-bit and 64-bit CPUs, system and user emulation 
> >                        mode, o32 user ABI,
> 
> I'm not sure if it's a good idea to change the meaning of linux-user
> qemu-mips64 and qemu-mips64el, this will cause unnecessary confusion in
> my opinion. I think we’d be better off leaving it consistent across QEMU
> versions.

 Well, this is an example how the names could have been consistent from 
the beginning, and I actually agree we need to take a notion of what's 
already there.  So alternatively these could be called `mips64o32' and 
`mips64o32el' though I find these names somewhat ugly.  Although perhaps 
not anymore if we kept what we have now for backwards compatibility and 
added a set of uniform target names like this:

- mips32o32|mips32o32el (or maybe just mipso32|mipso32el),

- mips64o32|mips64o32el,

- mips64n64|mips64n64el,

- mips64n32|mips64n32el.

Or maybe just the three latters, leaving mips|mipsel as it is.  WDYT?

> Do we really need MIPS64 executables for o32 ABI for linux-user? They
> would merely enable MIPS64 CPUs to run o32 programs. So far we've been
> handling this by using 32-bit CPUs (artificial if the real CPU don't
> exist), therefore I don't see an issue here. Also I'm concerned that
> once we add new executables, it will be difficult to revert that change
> later, thus we must be certain that this is the right way to go.

 There is a slight difference for some processors that do not have 32-bit 
counterparts.  Think of an o32 program run on an R10000 processor, or, to 
pick a more modern example, a Loongson-2E CPU.  I think NetLogic or Cavium 
implementations qualify here as well.  I don't think hacking QEMU sources 
to add even more artificial silicon is a good way to address these cases.

  Maciej

Re: [Qemu-devel] [PATCH v2 1/2] target-mips: Rework ABIs to allow all required configurations

[Peter Maydell]

Added RTH to cc because IIRC you did the last lot of rearranging how
we handle these "same CPU architecture, different ABI" variants of
linux-user...

On 9 February 2015 at 14:09, Maciej W. Rozycki <macro@linux-mips.org> wrote:
> On Mon, 9 Feb 2015, Leon Alrae wrote:
>
>> > Rework the MIPS ABIs and CPU emulations available according to the
>> > following target list:
>> >
>> > - mips|mipsel       -- 32-bit CPUs only, system and user emulation mode,
>> >                        o32 user ABI,
>> >
>> > - mips64|mips64el   -- 32-bit and 64-bit CPUs, system and user emulation
>> >                        mode, o32 user ABI,
>>
>> I'm not sure if it's a good idea to change the meaning of linux-user
>> qemu-mips64 and qemu-mips64el, this will cause unnecessary confusion in
>> my opinion. I think we’d be better off leaving it consistent across QEMU
>> versions.
>
>  Well, this is an example how the names could have been consistent from
> the beginning, and I actually agree we need to take a notion of what's
> already there.

I think "don't break executable names that are already present"
is a hard requirement. These get baked into binfmt-misc configurations
and effectively become part of QEMU's ABI to users.

> So alternatively these could be called `mips64o32' and
> `mips64o32el' though I find these names somewhat ugly.  Although perhaps
> not anymore if we kept what we have now for backwards compatibility and
> added a set of uniform target names like this:
>
> - mips32o32|mips32o32el (or maybe just mipso32|mipso32el),
>
> - mips64o32|mips64o32el,
>
> - mips64n64|mips64n64el,
>
> - mips64n32|mips64n32el.
>
> Or maybe just the three latters, leaving mips|mipsel as it is.  WDYT?

So which of these four does the current "mips64/mips64el" correspond
to? That's the third in the list, right? And the current mipsn32/mipsn32el
is the fourth? So this is adding alias names for our existing targets
and creating a new one? I think I'd just leave the current names and
define new target names where we need to.

If we could figure out and write down what the design principle
is for which targets to create to handle different ABIs in linux-user
that would be handy, because at some point I need to think about
this to handle the equivalent situation for ARM (a probable
upcoming ILP32 ABI, and what to do about running 32-bit code on
64-bit CPU definitions)...

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 1/2] target-mips: Rework ABIs to allow all required configurations

[Maciej W. Rozycki]

On Mon, 9 Feb 2015, Peter Maydell wrote:

> >> I'm not sure if it's a good idea to change the meaning of linux-user
> >> qemu-mips64 and qemu-mips64el, this will cause unnecessary confusion in
> >> my opinion. I think we’d be better off leaving it consistent across QEMU
> >> versions.
> >
> >  Well, this is an example how the names could have been consistent from
> > the beginning, and I actually agree we need to take a notion of what's
> > already there.
> 
> I think "don't break executable names that are already present"
> is a hard requirement. These get baked into binfmt-misc configurations
> and effectively become part of QEMU's ABI to users.

 Acknowledged, I do recognise and accept the requirement.

> > So alternatively these could be called `mips64o32' and
> > `mips64o32el' though I find these names somewhat ugly.  Although perhaps
> > not anymore if we kept what we have now for backwards compatibility and
> > added a set of uniform target names like this:
> >
> > - mips32o32|mips32o32el (or maybe just mipso32|mipso32el),
> >
> > - mips64o32|mips64o32el,
> >
> > - mips64n64|mips64n64el,
> >
> > - mips64n32|mips64n32el.
> >
> > Or maybe just the three latters, leaving mips|mipsel as it is.  WDYT?
> 
> So which of these four does the current "mips64/mips64el" correspond
> to? That's the third in the list, right? And the current mipsn32/mipsn32el
> is the fourth?

 Correct.

> So this is adding alias names for our existing targets
> and creating a new one? I think I'd just leave the current names and
> define new target names where we need to.

 What I have been a bit concerned of is how the way these names were added 
(i.e. in an incremental manner and not really architected) results in what 
looks like a random selection of arbitrary names that are all but obvious 
to the user.

 Only "mipsn32/mipsn32el" have any notion of the selected ABI in the name, 
but then they lack any emphasis that this is a 64-bit ABI.  The remaining 
two pairs, "mips/mipsel" and "mips64/mips64el", respectively refer to 
architecture names rather than a particular ABI, in the traditional sense 
(such as used by the GNU config.guess/config.sub scripts or reported by 
uname(2) on Linux) merely meaning 32-bit or 64-bit MIPS processors without 
any further implication as to the ABI (of course in the context of Linux a 
32-bit CPU cannot support anything but o32, but that's an indirect 
implication only).

 Of course ideally we'd have a single executable supporting all the ABIs 
and selecting the right one on the fly.  Or maybe two, to account for the 
two endiannesses, although being able to switch that at the run time so 
that a single "interpreter" handles all MIPS executables would be a great 
feature too.  But that's a differenr matter, and if such a unified 
configuration is ever implemented, then we can simply alias all the 
individual configuration names invented until then to one another.

> If we could figure out and write down what the design principle
> is for which targets to create to handle different ABIs in linux-user
> that would be handy, because at some point I need to think about
> this to handle the equivalent situation for ARM (a probable
> upcoming ILP32 ABI, and what to do about running 32-bit code on
> 64-bit CPU definitions)...

 I think this is as simple as following what hardware offers, under the 
assumption that we want to be able to reproduce a simulated user-mode 
environment just as it would look like on actual hardware.  This could be 
for any reason, I think performance in the first place as QEMU run on a 
decent host machine can often be much, much faster than actual target 
hardware, and then the inability to reproduce target hardware beyond the 
CPU or to run a real Linux kernel on such hardware in the system emulation 
mode.

 So referring to the MIPS target -- as one I'm the most familiar with -- 
we have a choice of 3 Linux user ABIs in both endiannesses each.  And then 
we have a bunch of processors we already simulate or the simulation of 
which can be added, often in a straightforward manner as lots of 
documentation is available.  And now I expect to be able to pick any 
compatible CPU-ABI pair and simulate it.  It should correctly simulate all 
the instructions CPU implements and correctly trap with SIGILL on all the 
instructions CPU does not implement.  It can then be used for example for 
toolchain correctness validation.

 I don't know exactly how ARM architecture subsetting has been defined, 
but with the MIPS architecture it has been the case that 32-bit additions 
were added to a 64-bit architecture.  Specifically the MIPS IV 
architecture, a 64-bit one, added several features to the MIPS III 
architecture, also a 64-bit one.  These were conditional move operations, 
extra floating-point condition bits, the indexed addressing mode for 
floating-point load/store instructions and cache prefetch instructions. 
These were naturally available for 32-bit aka o32 programs run in the 
32-bit compatibility user mode.  This is unlike any 64-bit instructions as 
these are not allowed in the 32-bit compatibility user mode and trap with 
a Reserved Instruction exception as if they were unimplemented.

 More recently there have been vendor-specific architecture extensions 
added to 64-bit processors, that also affect o32 executable environment.  
At least one of them -- the Lemote Loongson-2E processor -- has been 
publicly documented and we already have support for its extensions in 
place.  Other extensions can follow if the respective vendors decide to 
either contribute their implementation or at least publish the specs.

 So I think as far as the MIPS target is concerned it makes sense to have 
64-bit processors enabled for o32 programs.  And I think for performance 
reasons it makes sense to keep a configuration with only 32-bit processors 
enabled as well.

 Does it make the design principles I have in mind any clearer to you?

  Maciej