From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJK89-0004bu-Pt for qemu-devel@nongnu.org; Sun, 04 Nov 2018 10:16:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJK2S-0004P8-DW for qemu-devel@nongnu.org; Sun, 04 Nov 2018 10:10:11 -0500 Received: from eddie.linux-mips.org ([148.251.95.138]:59306 helo=cvs.linux-mips.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJK2S-0004MC-3e for qemu-devel@nongnu.org; Sun, 04 Nov 2018 10:10:08 -0500 Received: (from localhost user: 'macro', uid#1010) by eddie.linux-mips.org with ESMTP id S23990412AbeKDPJcZ2zaB (ORCPT ); Sun, 4 Nov 2018 16:09:32 +0100 Date: Sun, 4 Nov 2018 15:09:32 +0000 (GMT) Sender: "Maciej W. Rozycki" From: "Maciej W. Rozycki" In-Reply-To: <20181104131236.GA30862@sx9> Message-ID: References: <1001e61e-b6c0-1a41-9e9f-e2fd5a51f7b5@linaro.org> <20181104131236.GA30862@sx9> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Subject: Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fredrik Noring Cc: Richard Henderson , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Aurelien Jarno , =?UTF-8?Q?J=C3=BCrgen_Urban?= , qemu-devel@nongnu.org On Sun, 4 Nov 2018, Fredrik Noring wrote: > It appears the correct function is tcg_gen_mov_tl because the TX79 manual > says > > MFHI: GPR[rd]63..0 <- HI63..0 > MFLO: GPR[rd]63..0 <- LO63..0 > MTHI: HI63..0 <- GPR[rs]63..0 > MTLO: LO63..0 <- GPR[rs]63..0 > MFHI1: GPR[rd]63..0 <- HI127..64 > MFLO1: GPR[rd]63..0 <- LO127..64 > MTHI1: HI127..64 <- GPR[rs]63..0 > MTLO1: LO127..64 <- GPR[rs]63..0 > > so the GPR is copied to/from in full in all cases. This is slightly > different to how acc = 1 is handled in gen_HILO. However `gen_HILO' looks wrong to me as it'll truncate the values of $acc3-$acc1 with the 64-bit DSP ASE. Maciej