From: BALATON Zoltan <balaton@eik.bme.hu>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Nicholas Piggin" <npiggin@gmail.com>
Subject: Re: [PATCH 15/16] hw/pci-host/raven: Do not map regions in init method
Date: Tue, 3 Jun 2025 15:50:27 +0200 (CEST) [thread overview]
Message-ID: <alpine.LMD.2.03.2506031547560.13449@eik.bme.hu> (raw)
In-Reply-To: <bfd1359d-2a25-4c53-9eee-cec527197f8e@linaro.org>
[-- Attachment #1: Type: TEXT/PLAIN, Size: 5438 bytes --]
On Tue, 3 Jun 2025, Philippe Mathieu-Daudé wrote:
> On 4/5/25 18:01, BALATON Zoltan wrote:
>> Export memory regions as sysbus mmio regions and let the board code
>> map them.
>>
>
> Why? The mapping belong to the host bridge, not the board...
I took inspiration from grackle that does it the same way.
Regards,
BALATON Zoltan
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/pci-host/raven.c | 37 ++++++++++++-------------------------
>> hw/ppc/prep.c | 11 +++++++++--
>> 2 files changed, 21 insertions(+), 27 deletions(-)
>>
>> diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
>> index 68d64e3a97..c9df3db401 100644
>> --- a/hw/pci-host/raven.c
>> +++ b/hw/pci-host/raven.c
>> @@ -49,8 +49,6 @@ struct PREPPCIState {
>> AddressSpace bm_as;
>> };
>> -#define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus
>> */
>> -
>> static inline uint32_t raven_idsel_to_addr(hwaddr addr)
>> {
>> return (ctz16(addr >> 11) << 11) | (addr & 0x7ff);
>> @@ -166,7 +164,7 @@ static void raven_change_gpio(void *opaque, int n, int
>> level)
>> memory_region_set_enabled(&s->pci_discontiguous_io, !!level);
>> }
>> -static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>> +static void raven_pcihost_realize(DeviceState *d, Error **errp)
>> {
>> SysBusDevice *dev = SYS_BUS_DEVICE(d);
>> PCIHostState *h = PCI_HOST_BRIDGE(dev);
>> @@ -176,7 +174,17 @@ static void raven_pcihost_realizefn(DeviceState *d,
>> Error **errp)
>> qdev_init_gpio_in(d, raven_change_gpio, 1);
>> + memory_region_init(&s->pci_io, o, "pci-io", 0x3f800000);
>> + memory_region_init_io(&s->pci_discontiguous_io, o,
>> + &raven_io_ops, &s->pci_io,
>> + "pci-discontiguous-io", 8 * MiB);
>> + memory_region_init(&s->pci_memory, o, "pci-memory", 0x3f000000);
>> +
>> + sysbus_init_mmio(dev, &s->pci_io);
>> + sysbus_init_mmio(dev, &s->pci_discontiguous_io);
>> + sysbus_init_mmio(dev, &s->pci_memory);
>> sysbus_init_irq(dev, &s->irq);
>> +
>> h->bus = pci_register_root_bus(d, NULL, raven_set_irq, raven_map_irq,
>> &s->irq, &s->pci_memory, &s->pci_io,
>> 0, 1,
>> TYPE_PCI_BUS);
>> @@ -215,32 +223,12 @@ static void raven_pcihost_realizefn(DeviceState *d,
>> Error **errp)
>> pci_setup_iommu(h->bus, &raven_iommu_ops, s);
>> }
>> -static void raven_pcihost_initfn(Object *obj)
>> -{
>> - PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
>> - MemoryRegion *address_space_mem = get_system_memory();
>> -
>> - memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
>> - memory_region_init_io(&s->pci_discontiguous_io, obj,
>> - &raven_io_ops, &s->pci_io,
>> - "pci-discontiguous-io", 8 * MiB);
>> - memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
>> -
>> - /* CPU address space */
>> - memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
>> - &s->pci_io);
>> - memory_region_add_subregion_overlap(address_space_mem,
>> PCI_IO_BASE_ADDR,
>> - &s->pci_discontiguous_io, 1);
>> - memory_region_set_enabled(&s->pci_discontiguous_io, false);
>> - memory_region_add_subregion(address_space_mem, 0xc0000000,
>> &s->pci_memory);
>> -}
>> -
>> static void raven_pcihost_class_init(ObjectClass *klass, const void
>> *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
>> - dc->realize = raven_pcihost_realizefn;
>> + dc->realize = raven_pcihost_realize;
>> dc->fw_name = "pci";
>> }
>> @@ -274,7 +262,6 @@ static const TypeInfo raven_types[] = {
>> .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
>> .parent = TYPE_PCI_HOST_BRIDGE,
>> .instance_size = sizeof(PREPPCIState),
>> - .instance_init = raven_pcihost_initfn,
>> .class_init = raven_pcihost_class_init,
>> },
>> {
>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>> index d3365414d2..23d0e1eeaa 100644
>> --- a/hw/ppc/prep.c
>> +++ b/hw/ppc/prep.c
>> @@ -53,8 +53,11 @@
>> #define CFG_ADDR 0xf0000510
>> -#define KERNEL_LOAD_ADDR 0x01000000
>> -#define INITRD_LOAD_ADDR 0x01800000
>> +#define KERNEL_LOAD_ADDR 0x01000000
>> +#define INITRD_LOAD_ADDR 0x01800000
>> +
>> +#define PCI_IO_BASE_ADDR 0x80000000
>> +#define PCI_MEM_BASE_ADDR 0xc0000000
>> #define BIOS_ADDR 0xfff00000
>> #define BIOS_SIZE (1 * MiB)
>> @@ -293,6 +296,10 @@ static void ibm_40p_init(MachineState *machine)
>> pcihost = SYS_BUS_DEVICE(dev);
>> object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
>> sysbus_realize_and_unref(pcihost, &error_fatal);
>> + sysbus_mmio_map(pcihost, 0, PCI_IO_BASE_ADDR);
>> + sysbus_mmio_map_overlap(pcihost, 1, PCI_IO_BASE_ADDR, 1);
>> + memory_region_set_enabled(sysbus_mmio_get_region(pcihost, 1), false);
>> + sysbus_mmio_map(pcihost, 2, PCI_MEM_BASE_ADDR);
>> pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
>> if (!pci_bus) {
>> error_report("could not create PCI host controller");
>
>
next prev parent reply other threads:[~2025-06-03 13:51 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-04 16:01 [PATCH 00/16] hw/pci-host/raven clean ups BALATON Zoltan
2025-05-04 16:01 ` [PATCH 01/16] hw/pci-host/raven: Remove is-legacy-prep property BALATON Zoltan
2025-06-03 11:31 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 02/16] hw/pci-host/raven: Revert "raven: Move BIOS loading from board code to PCI host" BALATON Zoltan
2025-06-03 11:37 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 03/16] hw/pci-host/raven: Simplify PCI facing part BALATON Zoltan
2025-06-03 11:41 ` Philippe Mathieu-Daudé
2025-06-03 13:41 ` BALATON Zoltan
2025-05-04 16:01 ` [PATCH 04/16] hw/pci-host/raven: Simplify host bridge type declaration BALATON Zoltan
2025-06-03 11:41 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 05/16] hw/pci-host/raven: Use DEFINE_TYPES macro BALATON Zoltan
2025-06-03 11:42 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 06/16] hw/pci-host/raven: Simplify PCI bus creation BALATON Zoltan
2025-05-04 16:01 ` [PATCH 07/16] hw/pci-host/raven: Simplify PCI interrupt routing BALATON Zoltan
2025-05-04 16:01 ` [PATCH 08/16] hw/pci-host/raven: Simplify direct config access address decoding BALATON Zoltan
2025-05-04 16:01 ` [PATCH 09/16] hw/pci-host/raven: Rename direct config access ops BALATON Zoltan
2025-05-04 16:01 ` [PATCH 10/16] hw/pci-host/raven: Use correct parameter in direct " BALATON Zoltan
2025-06-03 11:47 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 11/16] hw/pci-host/raven: Do not use parent object for mmcfg region BALATON Zoltan
2025-06-03 11:50 ` Philippe Mathieu-Daudé
2025-06-03 13:45 ` BALATON Zoltan
2025-05-04 16:01 ` [PATCH 12/16] hw/pci-host/raven: Fix PCI config direct access region BALATON Zoltan
2025-06-03 11:52 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 13/16] hw/pci-host/raven: Simpify discontiguous IO access BALATON Zoltan
2025-05-04 16:01 ` [PATCH 14/16] hw/pci-host/raven: Move bus master address space creation to one place BALATON Zoltan
2025-05-04 16:01 ` [PATCH 15/16] hw/pci-host/raven: Do not map regions in init method BALATON Zoltan
2025-06-03 11:54 ` Philippe Mathieu-Daudé
2025-06-03 13:50 ` BALATON Zoltan [this message]
2025-06-04 10:39 ` Philippe Mathieu-Daudé
2025-05-04 16:01 ` [PATCH 16/16] hw/ppc/prep: Fix non-contiguous IO control bit BALATON Zoltan
2025-05-22 22:31 ` [PATCH 00/16] hw/pci-host/raven clean ups BALATON Zoltan
2025-06-02 12:27 ` BALATON Zoltan
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