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From: "Daniel P. Berrangé" <berrange@redhat.com>
To: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
Cc: Bin Meng <bin.meng@processmission.com>,
	QEMU <qemu-devel@nongnu.org>, Conor Dooley <conor@kernel.org>,
	Markus Armbruster <armbru@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
	Thomas Huth <th.huth@posteo.eu>,
	Paolo Bonzini <pbonzini@redhat.com>,
	BALATON Zoltan <balaton@eik.bme.hu>
Subject: Re: [PATCH v4 27/27] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer
Date: Wed, 14 Oct 2026 09:06:12 +0100	[thread overview]
Message-ID: <as839M8VjrWh4r2-@redhat.com> (raw)
In-Reply-To: <72240455-9409-491e-84fe-f29efb7187a6@oss.qualcomm.com>

On Wed, Oct 14, 2026 at 06:16:27AM +0200, Philippe Mathieu-Daudé wrote:
> On 14/10/26 03:23, Bin Meng wrote:
> > Conor asked not to be listed as a maintainer, since that could imply
> > that Microchip sponsors his work on the platform.
> 
> Hmm we hit a limitation of MAINTAINERS format.

I guess they're concerned about "Supported" vs "Maintained" as
the subsystem status

   Supported:   Someone is actually paid to look after this.
   Maintained:  Someone actually looks after it.

Technically that language means you should not assume that
all listed M: are paid - only that at least 1 M: is a paid
maintainer.  IMHO since Conor uses a non-corporate email
address there's even less reason to assume they're doing it
in a paid maintainer role, as opposed to volunteer.


> If so, the Sebastian is in the same situation.
> 
> (we had a similar case with PIIX3:hobbyist / PIIX4:cloud in the past)
> 
> > 
> > Keep him listed as a reviewer so he continues to receive relevant
> > patches without suggesting an active maintenance commitment.
> > 
> > Suggested-by: Conor Dooley <conor@kernel.org>
> > Signed-off-by: Bin Meng <bin.meng@processmission.com>
> > Acked-by: Conor Dooley <conor@kernel.org>
> > 
> > 
> > ---
> > 
> > (no changes since v2)
> > 
> > Changes in v2:
> > - New
> > 
> >   MAINTAINERS | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 0edc7385fd..40232cb65e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1794,8 +1794,8 @@ F: tests/tcg/riscv64/test-crc32.S
> >   Microchip PolarFire SoC Icicle Kit
> >   M: Bin Meng <bin.meng@processmission.com>
> > -M: Conor Dooley <conor@kernel.org>
> >   M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> > +R: Conor Dooley <conor@kernel.org>
> >   L: qemu-riscv@nongnu.org
> >   S: Supported
> >   F: docs/system/riscv/microchip-icicle-kit.rst
> 
> Is tooling confused when we define the same section twice?
> 
> Microchip PolarFire SoC Icicle Kit
> M: Bin Meng <bin.meng@processmission.com>
> S: Supported
> F: docs/system/riscv/microchip-icicle-kit.rst
> F: hw/riscv/microchip_pfsoc.c
> F: hw/char/mchp_pfsoc_mmuart.c
> F: hw/misc/mchp_pfsoc_dmc.c
> F: hw/misc/mchp_pfsoc_ioscb.c
> F: hw/misc/mchp_pfsoc_sysreg.c
> F: include/hw/riscv/microchip_pfsoc.h
> F: include/hw/char/mchp_pfsoc_mmuart.h
> F: include/hw/misc/mchp_pfsoc_dmc.h
> F: include/hw/misc/mchp_pfsoc_ioscb.h
> F: include/hw/misc/mchp_pfsoc_sysreg.h
> 
> Microchip PolarFire SoC Icicle Kit
> M: Conor Dooley <conor@kernel.org>
> M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> S: Odd Fixes
> F: docs/system/riscv/microchip-icicle-kit.rst
> F: hw/riscv/microchip_pfsoc.c
> F: hw/char/mchp_pfsoc_mmuart.c
> F: hw/misc/mchp_pfsoc_dmc.c
> F: hw/misc/mchp_pfsoc_ioscb.c
> F: hw/misc/mchp_pfsoc_sysreg.c
> F: include/hw/riscv/microchip_pfsoc.h
> F: include/hw/char/mchp_pfsoc_mmuart.h
> F: include/hw/misc/mchp_pfsoc_dmc.h
> F: include/hw/misc/mchp_pfsoc_ioscb.h
> F: include/hw/misc/mchp_pfsoc_sysreg.h
> 

With regards,
Daniel
-- 
|: https://berrange.com       ~~        https://hachyderm.io/@berrange :|
|: https://libvirt.org          ~~          https://entangle-photo.org :|
|: https://pixelfed.art/berrange   ~~    https://fstop138.berrange.com :|



  reply	other threads:[~2026-10-14  8:06 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-14  1:22 [PATCH v4 00/27] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-10-14  1:22 ` [PATCH v4 01/27] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14  1:22 ` [PATCH v4 02/27] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-10-14  1:22 ` [PATCH v4 03/27] hw/misc: pfsoc: Support DDR training with newer HSS Bin Meng
2026-10-14  1:22 ` [PATCH v4 04/27] hw/misc: Add SiFive L2 cache controller model Bin Meng
2026-10-23  1:06   ` Chao Liu
2026-10-14  1:22 ` [PATCH v4 05/27] hw/riscv: pfsoc: Map the SiFive L2CC memory windows Bin Meng
2026-10-14  1:22 ` [PATCH v4 06/27] hw/riscv: sifive_u: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14  1:22 ` [PATCH v4 07/27] hw/riscv: sifive_u: Use the shared SiFive L2 cache controller Bin Meng
2026-10-14  1:22 ` [PATCH v4 08/27] tests/qtest: Add SiFive L2 cache controller coverage Bin Meng
2026-10-14  1:22 ` [PATCH v4 09/27] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-10-14  1:22 ` [PATCH v4 10/27] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer Bin Meng
2026-10-14  1:22 ` [PATCH v4 11/27] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-10-14  1:22 ` [PATCH v4 12/27] hw/sd: cadence: Add 64-bit system bus property Bin Meng
2026-10-14  1:22 ` [PATCH v4 13/27] hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support Bin Meng
2026-10-14  1:22 ` [PATCH v4 14/27] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-10-14  1:22 ` [PATCH v4 15/27] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-10-14  1:22 ` [PATCH v4 16/27] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-10-14  1:22 ` [PATCH v4 17/27] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-10-14  1:22 ` [PATCH v4 18/27] hw/misc: pfsoc: Honor service notification requests Bin Meng
2026-10-14  1:22 ` [PATCH v4 19/27] hw/misc: pfsoc: Let IOSCB own service interrupt state Bin Meng
2026-10-14  1:23 ` [PATCH v4 20/27] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-10-14  1:23 ` [PATCH v4 21/27] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-10-14  1:23 ` [PATCH v4 22/27] hw/riscv: pfsoc: Default Icicle Kit to five harts Bin Meng
2026-10-14  1:23 ` [PATCH v4 23/27] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-10-14  1:23 ` [PATCH v4 24/27] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-10-14  1:23 ` [PATCH v4 25/27] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-10-14  1:23 ` [PATCH v4 26/27] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-10-14  1:23 ` [PATCH v4 27/27] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer Bin Meng
2026-10-14  4:16   ` Philippe Mathieu-Daudé
2026-10-14  8:06     ` Daniel P. Berrangé [this message]
2026-10-21  9:36 ` [PATCH v4 00/27] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng

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