* [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups
@ 2024-05-01 23:43 BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
` (28 more replies)
0 siblings, 29 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This series does some further clean up mostly around BookE MMU to
untangle it from other MMU models. It also contains some other changes
that I've come up with while working on this. The first 3 patches are
from the last exception handling clean up series that were dropped due
to some error on CI but I'm not sure if that was because of some CI
infrastructure problem or some problem with the patches as the error
did not make much sense. So these patches are only rebased now, I made
no other change to them until the issue is understood better. The rest
are new patches I've added since tha last series. Please review.
v2:
- Fix user mode issue in patch 1 by keeping old behaviour for user mode
- Add some more MMU clean up patches
Regards,
BALATON Zoltan
BALATON Zoltan (28):
target/ppc: Fix gen_sc to use correct nip
target/ppc: Move patching nip from exception handler to helper_scv
target/ppc: Simplify syscall exception handlers
target/ppc: Remove unused helper
target/ppc/mmu_common.c: Move calculation of a value closer to its
usage
target/ppc/mmu_common.c: Move calculation of a value closer to its
usage
target/ppc/mmu_common.c: Remove unneeded local variable
target/ppc/mmu_common.c: Simplify checking for real mode
target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU
target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()
target/ppc/mmu_common.c: Rename get_bat_6xx_tlb()
target/ppc/mmu_common.c: Split out BookE cases before checking real
mode
target/ppc/mmu_common.c: Split off real mode cases in
get_physical_address_wtlb()
target/ppc/mmu_common.c: Inline and remove check_physical()
target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address()
target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address()
target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls
target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
target/ppc/mmu_common.c: Replace hard coded constants in
ppc_jumbo_xlate()
target/ppc/mmu_common.c: Make get_physical_address_wtlb() static
target/ppc: Move mmu_ctx_t definition to mmu_common.c
target/ppc: Remove ppc_hash32_pp_prot() and reuse common function
target/ppc/mmu_common.c: Split off BookE handling from
ppc_jumbo_xlate()
target/ppc/mmu_common.c: Remove BookE handling from
get_physical_address_wtlb()
target/ppc/mmu_common.c: Simplify ppc_booke_xlate()
target/ppc/mmu_common.c: Move BookE MMU functions together
target/ppc: Remove id_tlbs flag from CPU env
target/ppc: Split off common 4xx TLB init
hw/ppc/pegasos2.c | 2 +-
target/ppc/cpu.h | 1 -
target/ppc/cpu_init.c | 65 ++--
target/ppc/excp_helper.c | 67 +---
target/ppc/helper.h | 2 -
target/ppc/helper_regs.c | 1 -
target/ppc/internal.h | 19 +-
target/ppc/mmu-hash32.c | 47 +--
target/ppc/mmu_common.c | 792 +++++++++++++++++++--------------------
target/ppc/mmu_helper.c | 36 +-
target/ppc/translate.c | 21 +-
11 files changed, 438 insertions(+), 615 deletions(-)
--
2.30.9
^ permalink raw reply [flat|nested] 66+ messages in thread
* [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
` (27 subsequent siblings)
28 siblings, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Most exceptions are raised with nip pointing to the faulting
instruction but the sc instruction generating a syscall exception
leaves nip pointing to next instruction. Fix gen_sc to not use
gen_exception_err() which sets nip back but correctly set nip to
pc_next so we don't have to patch this in the exception handlers.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/excp_helper.c | 43 ++--------------------------------------
target/ppc/translate.c | 15 ++++++--------
2 files changed, 8 insertions(+), 50 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0712098cf7..92fe535815 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -116,7 +116,7 @@ static void dump_syscall(CPUPPCState *env)
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
- ppc_dump_gpr(env, 8), env->nip);
+ ppc_dump_gpr(env, 8), env->nip - 4);
}
static void dump_hcall(CPUPPCState *env)
@@ -131,7 +131,7 @@ static void dump_hcall(CPUPPCState *env)
ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
- env->nip);
+ env->nip - 4);
}
#ifdef CONFIG_TCG
@@ -516,12 +516,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
trace_ppc_excp_print("FIT");
@@ -632,12 +626,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
@@ -780,13 +768,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
@@ -932,13 +913,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
@@ -1098,12 +1072,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
@@ -1428,13 +1396,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/* "PAPR mode" built-in hypercall emulation */
if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
PPCVirtualHypervisorClass *vhc =
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 93ffec787c..e112c44a02 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4472,22 +4472,19 @@ static void gen_hrfid(DisasContext *ctx)
#endif
/* sc */
-#if defined(CONFIG_USER_ONLY)
-#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
-#else
-#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
-#endif
static void gen_sc(DisasContext *ctx)
{
- uint32_t lev;
-
/*
* LEV is a 7-bit field, but the top 6 bits are treated as a reserved
* field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
* for Ultravisor which TCG does not support, so just ignore the top 6.
*/
- lev = (ctx->opcode >> 5) & 0x1;
- gen_exception_err(ctx, POWERPC_SYSCALL, lev);
+ uint32_t lev = (ctx->opcode >> 5) & 0x1;
+#ifdef CONFIG_USER_ONLY
+ gen_exception_err(ctx, POWERPC_EXCP_SYSCALL_USER, lev);
+#else
+ gen_exception_err_nip(ctx, POWERPC_EXCP_SYSCALL, lev, ctx->base.pc_next);
+#endif
}
#if defined(TARGET_PPC64)
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers BALATON Zoltan
` (26 subsequent siblings)
28 siblings, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
From: Nicholas Piggin <npiggin@gmail.com>
Unlike sc, for scv a facility unavailable interrupt must be generated
if FSCR[SCV]=0 so we can't raise the exception with nip set to next
instruction but we can move advancing nip if the FSCR check passes to
helper_scv so the exception handler does not need to change it.
[balaton: added commit message]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/excp_helper.c | 2 +-
target/ppc/translate.c | 6 +++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 92fe535815..5aa84bccd2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1415,7 +1415,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
lev = env->error_code;
dump_syscall(env);
- env->nip += 4;
new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
@@ -2524,6 +2523,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env)
void helper_scv(CPUPPCState *env, uint32_t lev)
{
if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
+ env->nip += 4;
raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
} else {
raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e112c44a02..1d4e9f0679 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4493,7 +4493,11 @@ static void gen_scv(DisasContext *ctx)
{
uint32_t lev = (ctx->opcode >> 5) & 0x7F;
- /* Set the PC back to the faulting instruction. */
+ /*
+ * Set the PC back to the scv instruction (unlike sc), because a facility
+ * unavailable interrupt must be generated if FSCR[SCV]=0. The helper
+ * advances nip if the FSCR check passes.
+ */
gen_update_nip(ctx, ctx->cia);
gen_helper_scv(tcg_env, tcg_constant_i32(lev));
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
` (25 subsequent siblings)
28 siblings, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
After previous changes the hypercall handling in 7xx and 74xx
exception handlers can be folded into one if statement to simplify
this code. Also add "unlikely" to mark the less frequently used branch
for the compiler.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5aa84bccd2..d19212f772 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -762,26 +762,21 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL: /* System call exception */
{
int lev = env->error_code;
-
- if (lev == 1 && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
* uses VOF and the 7xx CPUs, so although the 7xx don't have
* HV mode, we need to keep hypercall support.
*/
- if (lev == 1 && cpu->vhyp) {
+ if (unlikely(lev == 1 && cpu->vhyp)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ dump_hcall(env);
vhc->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
return;
}
-
+ dump_syscall(env);
break;
}
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
@@ -907,26 +902,21 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL: /* System call exception */
{
int lev = env->error_code;
-
- if (lev == 1 && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
* uses VOF and the 74xx CPUs, so although the 74xx don't have
* HV mode, we need to keep hypercall support.
*/
- if (lev == 1 && cpu->vhyp) {
+ if (unlikely(lev == 1 && cpu->vhyp)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ dump_hcall(env);
vhc->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
return;
}
-
+ dump_syscall(env);
break;
}
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 04/28] target/ppc: Remove unused helper
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (2 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:18 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
` (24 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
The helper_rac function is defined but not used, remove it.
Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/helper.h | 2 --
target/ppc/mmu_helper.c | 24 ------------------------
2 files changed, 26 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 86f97ee1e7..f769e01c3d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -700,8 +700,6 @@ DEF_HELPER_2(book3s_msgclr, void, env, tl)
DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32)
#if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_2(rac, tl, env, tl)
-
DEF_HELPER_2(load_dcr, tl, env, tl)
DEF_HELPER_3(store_dcr, void, env, tl, tl)
#endif
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index c071b4d5e2..817836b731 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -595,30 +595,6 @@ void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN)
do_6xx_tlb(env, EPN, 1);
}
-/*****************************************************************************/
-/* PowerPC 601 specific instructions (POWER bridge) */
-
-target_ulong helper_rac(CPUPPCState *env, target_ulong addr)
-{
- mmu_ctx_t ctx;
- int nb_BATs;
- target_ulong ret = 0;
-
- /*
- * We don't have to generate many instances of this instruction,
- * as rac is supervisor only.
- *
- * XXX: FIX THIS: Pretend we have no BAT
- */
- nb_BATs = env->nb_BATs;
- env->nb_BATs = 0;
- if (get_physical_address_wtlb(env, &ctx, addr, 0, ACCESS_INT, 0) == 0) {
- ret = ctx.raddr;
- }
- env->nb_BATs = nb_BATs;
- return ret;
-}
-
static inline target_ulong booke_tlb_to_page_size(int size)
{
return 1024 << (2 * size);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (3 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:19 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
` (23 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
In mmubooke_check_tlb() prot2 is calculated first but only used after
an unrelated check that can return before tha value is used. Move the
calculation after the check, closer to where it is used, to keep them
together and avoid computing it when not needed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 751403f1c8..168ff842a5 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -634,12 +634,6 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
return -1;
}
- if (FIELD_EX64(env->msr, MSR, PR)) {
- prot2 = tlb->prot & 0xF;
- } else {
- prot2 = (tlb->prot >> 4) & 0xF;
- }
-
/* Check the address space */
if ((access_type == MMU_INST_FETCH ?
FIELD_EX64(env->msr, MSR, IR) :
@@ -648,6 +642,11 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
return -1;
}
+ if (FIELD_EX64(env->msr, MSR, PR)) {
+ prot2 = tlb->prot & 0xF;
+ } else {
+ prot2 = (tlb->prot >> 4) & 0xF;
+ }
*prot = prot2;
if (prot2 & prot_for_access_type(access_type)) {
qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 06/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (4 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:20 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
` (22 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
In mmubooke206_check_tlb() prot2 is calculated first but only used
after an unrelated check that can return before tha value is used.
Move the calculation after the check, closer to where it is used, to
keep them together and avoid computing it when not needed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 168ff842a5..b0aca8ec02 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -828,6 +828,18 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
found_tlb:
+ /* Check the address space and permissions */
+ if (access_type == MMU_INST_FETCH) {
+ /* There is no way to fetch code using epid load */
+ assert(!use_epid);
+ as = FIELD_EX64(env->msr, MSR, IR);
+ }
+
+ if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
+ qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
+ return -1;
+ }
+
if (pr) {
if (tlb->mas7_3 & MAS3_UR) {
prot2 |= PAGE_READ;
@@ -849,19 +861,6 @@ found_tlb:
prot2 |= PAGE_EXEC;
}
}
-
- /* Check the address space and permissions */
- if (access_type == MMU_INST_FETCH) {
- /* There is no way to fetch code using epid load */
- assert(!use_epid);
- as = FIELD_EX64(env->msr, MSR, IR);
- }
-
- if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
- qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
- return -1;
- }
-
*prot = prot2;
if (prot2 & prot_for_access_type(access_type)) {
qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (5 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:30 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
` (21 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
value directly the the destination, no need to have a separate local
variable for it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index b0aca8ec02..74c3b814c9 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -627,8 +627,6 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
hwaddr *raddr, int *prot, target_ulong address,
MMUAccessType access_type, int i)
{
- int prot2;
-
if (!mmubooke_check_pid(env, tlb, raddr, address, i)) {
qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__);
return -1;
@@ -643,17 +641,16 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
}
if (FIELD_EX64(env->msr, MSR, PR)) {
- prot2 = tlb->prot & 0xF;
+ *prot = tlb->prot & 0xF;
} else {
- prot2 = (tlb->prot >> 4) & 0xF;
+ *prot = (tlb->prot >> 4) & 0xF;
}
- *prot = prot2;
- if (prot2 & prot_for_access_type(access_type)) {
+ if (*prot & prot_for_access_type(access_type)) {
qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
return 0;
}
- qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
+ qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot);
return access_type == MMU_INST_FETCH ? -3 : -2;
}
@@ -794,7 +791,6 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
- int prot2 = 0;
uint32_t epid;
bool as, pr;
bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
@@ -840,34 +836,34 @@ found_tlb:
return -1;
}
+ *prot = 0;
if (pr) {
if (tlb->mas7_3 & MAS3_UR) {
- prot2 |= PAGE_READ;
+ *prot |= PAGE_READ;
}
if (tlb->mas7_3 & MAS3_UW) {
- prot2 |= PAGE_WRITE;
+ *prot |= PAGE_WRITE;
}
if (tlb->mas7_3 & MAS3_UX) {
- prot2 |= PAGE_EXEC;
+ *prot |= PAGE_EXEC;
}
} else {
if (tlb->mas7_3 & MAS3_SR) {
- prot2 |= PAGE_READ;
+ *prot |= PAGE_READ;
}
if (tlb->mas7_3 & MAS3_SW) {
- prot2 |= PAGE_WRITE;
+ *prot |= PAGE_WRITE;
}
if (tlb->mas7_3 & MAS3_SX) {
- prot2 |= PAGE_EXEC;
+ *prot |= PAGE_EXEC;
}
}
- *prot = prot2;
- if (prot2 & prot_for_access_type(access_type)) {
+ if (*prot & prot_for_access_type(access_type)) {
qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
return 0;
}
- qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
+ qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot);
return access_type == MMU_INST_FETCH ? -3 : -2;
}
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (6 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:34 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
` (20 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
In get_physical_address_wtlb() the real_mode flag depends on either
the MSR[IR] or MSR[DR] bit depending on access_type. Extract just the
needed bit in a more straight forward way instead of doing unnecessary
computation.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 74c3b814c9..45b6501ecb 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1183,8 +1183,10 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
int mmu_idx)
{
int ret = -1;
- bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR)) ||
- (type != ACCESS_CODE && !FIELD_EX64(env->msr, MSR, DR));
+ bool real_mode;
+
+ real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
+ : !FIELD_EX64(env->msr, MSR, DR);
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (7 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:36 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
` (19 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
The default case will catch this and abort the same way and there is
still a warning about it in ppc_tlb_invalidate_all() so drop these
from mmu_common.c to simplify this code.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 45b6501ecb..98730035b1 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1218,10 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
mmu_idx);
break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
- break;
case POWERPC_MMU_REAL:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
@@ -1352,8 +1348,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
break;
- case POWERPC_MMU_MPC8xx:
- cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
@@ -1426,9 +1420,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
/* fall through */
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (8 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:42 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
` (18 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Repurpose get_segment_6xx_tlb() to do the whole address translation
for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
renaming it to match other similar functions. These are only called
once together so no need to keep these separate functions and
combining them simplifies the caller allowing further restructuring.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 98730035b1..ef1669b01d 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -359,19 +359,25 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
-/* Perform segment based translation */
-static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, MMUAccessType access_type,
- int type)
+static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr,
+ MMUAccessType access_type, int type)
{
PowerPCCPU *cpu = env_archcpu(env);
hwaddr hash;
- target_ulong vsid;
- int ds, target_page_bits;
+ target_ulong vsid, sr, pgidx;
bool pr;
- int ret;
- target_ulong sr, pgidx;
+ int ds, target_page_bits, ret = -1;
+ /* First try to find a BAT entry if there are any */
+ if (env->nb_BATs != 0) {
+ ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
+ }
+ if (ret >= 0) {
+ return ret;
+ }
+
+ /* Perform segment based translation when no BATs matched */
pr = FIELD_EX64(env->msr, MSR, PR);
ctx->eaddr = eaddr;
@@ -1193,14 +1199,8 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
} else {
- /* Try to find a BAT */
- if (env->nb_BATs != 0) {
- ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
- }
- if (ret < 0) {
- /* We didn't match any BAT entry or don't have BATs */
- ret = get_segment_6xx_tlb(env, ctx, eaddr, access_type, type);
- }
+ ret = mmu6xx_get_physical_address(env, ctx, eaddr, access_type,
+ type);
}
break;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (9 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:43 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
` (17 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Rename to ppc6xx_tlb_get_bat() to match other similar names in the
same file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index ef1669b01d..a069e4083f 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -288,8 +288,8 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
*protp = prot;
}
-static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong virtual, MMUAccessType access_type)
+static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, MMUAccessType access_type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong BEPIl, BEPIu, bl;
@@ -371,7 +371,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
/* First try to find a BAT entry if there are any */
if (env->nb_BATs != 0) {
- ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
+ ret = ppc6xx_tlb_get_bat(env, ctx, eaddr, access_type);
}
if (ret >= 0) {
return ret;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (10 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:50 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
` (16 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
BookE does not have real mode so split off and handle it first in
get_physical_address_wtlb() before checking for real mode for other
MMU models.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index a069e4083f..24a9b9ef19 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1191,6 +1191,13 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
int ret = -1;
bool real_mode;
+ if (env->mmu_model == POWERPC_MMU_BOOKE) {
+ return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
+ } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
+ return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
+ mmu_idx);
+ }
+
real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
: !FIELD_EX64(env->msr, MSR, DR);
@@ -1211,13 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
ret = mmu40x_get_physical_address(env, ctx, eaddr, access_type);
}
break;
- case POWERPC_MMU_BOOKE:
- ret = mmubooke_get_physical_address(env, ctx, eaddr, access_type);
- break;
- case POWERPC_MMU_BOOKE206:
- ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
- mmu_idx);
- break;
case POWERPC_MMU_REAL:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (11 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 9:58 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
` (15 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
The real mode handling is identical in the remaining switch cases.
Split off these common real mode cases into a separate conditional to
leave only the else branches in the switch that are different.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 34 +++++++++-------------------------
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 24a9b9ef19..3132030baa 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1188,7 +1188,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
MMUAccessType access_type, int type,
int mmu_idx)
{
- int ret = -1;
bool real_mode;
if (env->mmu_model == POWERPC_MMU_BOOKE) {
@@ -1200,38 +1199,23 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
: !FIELD_EX64(env->msr, MSR, DR);
+ if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
+ env->mmu_model == POWERPC_MMU_SOFT_4xx ||
+ env->mmu_model == POWERPC_MMU_REAL)) {
+ return check_physical(env, ctx, eaddr, access_type);
+ }
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, access_type);
- } else {
- ret = mmu6xx_get_physical_address(env, ctx, eaddr, access_type,
- type);
- }
- break;
-
+ return mmu6xx_get_physical_address(env, ctx, eaddr, access_type, type);
case POWERPC_MMU_SOFT_4xx:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, access_type);
- } else {
- ret = mmu40x_get_physical_address(env, ctx, eaddr, access_type);
- }
- break;
+ return mmu40x_get_physical_address(env, ctx, eaddr, access_type);
case POWERPC_MMU_REAL:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, access_type);
- } else {
- cpu_abort(env_cpu(env),
- "PowerPC in real mode do not do any translation\n");
- }
- return -1;
+ cpu_abort(env_cpu(env),
+ "PowerPC in real mode do not do any translation\n");
default:
cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n");
- return -1;
}
-
- return ret;
}
static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (12 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:00 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
` (14 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This function just does two assignments and and unnecessary check that
is always true so inline it in the only caller left and remove it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 26 +++-----------------------
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 3132030baa..fab86a8f3e 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1161,28 +1161,6 @@ void dump_mmu(CPUPPCState *env)
}
}
-static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
- MMUAccessType access_type)
-{
- ctx->raddr = eaddr;
- ctx->prot = PAGE_READ | PAGE_EXEC;
-
- switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_REAL:
- case POWERPC_MMU_BOOKE:
- ctx->prot |= PAGE_WRITE;
- break;
-
- default:
- /* Caller's checks mean we should never get here for other models */
- g_assert_not_reached();
- }
-
- return 0;
-}
-
int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr,
MMUAccessType access_type, int type,
@@ -1202,7 +1180,9 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
env->mmu_model == POWERPC_MMU_SOFT_4xx ||
env->mmu_model == POWERPC_MMU_REAL)) {
- return check_physical(env, ctx, eaddr, access_type);
+ ctx->raddr = eaddr;
+ ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return 0;
}
switch (env->mmu_model) {
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (13 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:03 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
` (13 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index fab86a8f3e..760e4072b2 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -665,31 +665,24 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
MMUAccessType access_type)
{
ppcemb_tlb_t *tlb;
- hwaddr raddr;
- int i, ret;
+ hwaddr raddr = (hwaddr)-1ULL;
+ int i, ret = -1;
- ret = -1;
- raddr = (hwaddr)-1ULL;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
access_type, i);
if (ret != -1) {
+ if (ret >= 0) {
+ ctx->raddr = raddr;
+ }
break;
}
}
-
- if (ret >= 0) {
- ctx->raddr = raddr;
- qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " HWADDR_FMT_plx " %d %d\n", __func__,
- address, ctx->raddr, ctx->prot, ret);
- } else {
- qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " HWADDR_FMT_plx " %d %d\n", __func__,
- address, raddr, ctx->prot, ret);
- }
-
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
+ " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
+ address, raddr, ctx->prot, ret);
return ret;
}
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (14 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:04 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
` (12 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This function is similar to mmubooke_get_physical_address() and can be
simplified the same way.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 760e4072b2..ebf18a751c 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -872,15 +872,11 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
int mmu_idx)
{
ppcmas_tlb_t *tlb;
- hwaddr raddr;
- int i, j, ret;
-
- ret = -1;
- raddr = (hwaddr)-1ULL;
+ hwaddr raddr = (hwaddr)-1ULL;
+ int i, j, ways, ret = -1;
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
- int ways = booke206_tlb_ways(env, i);
-
+ ways = booke206_tlb_ways(env, i);
for (j = 0; j < ways; j++) {
tlb = booke206_get_tlbm(env, i, address, j);
if (!tlb) {
@@ -889,6 +885,9 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
access_type, mmu_idx);
if (ret != -1) {
+ if (ret >= 0) {
+ ctx->raddr = raddr;
+ }
goto found_tlb;
}
}
@@ -896,17 +895,10 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
found_tlb:
- if (ret >= 0) {
- ctx->raddr = raddr;
- qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
- ctx->raddr, ctx->prot, ret);
- } else {
- qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
- raddr, ctx->prot, ret);
- }
-
+ qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
+ HWADDR_FMT_plx " %d %d\n", __func__,
+ ret < 0 ? "refused" : "granted", address, raddr,
+ ctx->prot, ret);
return ret;
}
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (15 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:05 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
` (11 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Fix several qemu_log_mask() calls that are misindented.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 42 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index ebf18a751c..28847c32f2 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -297,8 +297,8 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
int ret = -1;
bool ifetch = access_type == MMU_INST_FETCH;
- qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
- ifetch ? 'I' : 'D', virtual);
+ qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
+ ifetch ? 'I' : 'D', virtual);
if (ifetch) {
BATlt = env->IBAT[1];
BATut = env->IBAT[0];
@@ -312,9 +312,9 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
- qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
- TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
- ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
+ qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
+ TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
+ ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */
@@ -346,12 +346,11 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
- qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v "
- TARGET_FMT_lx " BATu " TARGET_FMT_lx
- " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
- TARGET_FMT_lx " " TARGET_FMT_lx "\n",
- __func__, ifetch ? 'I' : 'D', i, virtual,
- *BATu, *BATl, BEPIu, BEPIl, bl);
+ qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx
+ " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx
+ "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " "
+ TARGET_FMT_lx "\n", __func__, ifetch ? 'I' : 'D',
+ i, virtual, *BATu, *BATl, BEPIu, BEPIl, bl);
}
}
}
@@ -400,9 +399,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
hash = vsid ^ pgidx;
ctx->ptem = (vsid << 7) | (pgidx >> 10);
- qemu_log_mask(CPU_LOG_MMU,
- "pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
- ctx->key, ds, ctx->nx, vsid);
+ qemu_log_mask(CPU_LOG_MMU, "pte segment: key=%d ds %d nx %d vsid "
+ TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid);
ret = -1;
if (!ds) {
/* Check if instruction fetch is allowed, if needed */
@@ -599,9 +597,9 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
return 0;
}
}
- qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " HWADDR_FMT_plx
- " %d %d\n", __func__, address, raddr, ctx->prot, ret);
+ qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
+ " => " HWADDR_FMT_plx " %d %d\n",
+ __func__, address, raddr, ctx->prot, ret);
return ret;
}
@@ -713,11 +711,11 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
}
mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
- qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
- " PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
- HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
- __func__, address, pid, tlb->mas1, tlb->mas2, mask,
- tlb->mas7_3, tlb->mas8);
+ qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
+ " PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
+ HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
+ __func__, address, pid, tlb->mas1, tlb->mas2, mask,
+ tlb->mas7_3, tlb->mas8);
/* Check PID */
tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (16 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:06 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
` (10 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 319 ++++++++++++++++++++--------------------
1 file changed, 159 insertions(+), 160 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 28847c32f2..2487b4deff 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1265,187 +1265,186 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
*protp = ctx.prot;
*psizep = TARGET_PAGE_BITS;
return true;
+ } else if (!guest_visible) {
+ return false;
}
- if (guest_visible) {
- log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
- if (type == ACCESS_CODE) {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_6xx:
- cs->exception_index = POWERPC_EXCP_IFTLB;
- env->error_code = 1 << 18;
- env->spr[SPR_IMISS] = eaddr;
- env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
- goto tlb_miss;
- case POWERPC_MMU_SOFT_4xx:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- env->spr[SPR_40x_ESR] = 0x00000000;
- break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(cs, "PowerPC in real mode should never raise "
- "any MMU exceptions\n");
- default:
- cpu_abort(cs, "Unknown or invalid MMU model\n");
- }
+ log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+ if (type == ACCESS_CODE) {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ cs->exception_index = POWERPC_EXCP_IFTLB;
+ env->error_code = 1 << 18;
+ env->spr[SPR_IMISS] = eaddr;
+ env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
+ goto tlb_miss;
+ case POWERPC_MMU_SOFT_4xx:
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->error_code = 0;
+ env->spr[SPR_40x_DEAR] = eaddr;
+ env->spr[SPR_40x_ESR] = 0x00000000;
break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
- } else {
- env->error_code = 0x08000000;
- }
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
break;
- case -3:
- /* No execute protection violation */
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_ESR] = 0x00000000;
- env->error_code = 0;
+ case POWERPC_MMU_REAL:
+ cpu_abort(cs, "PowerPC in real mode should never raise "
+ "any MMU exceptions\n");
+ default:
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x08000000;
+ }
+ break;
+ case -3:
+ /* No execute protection violation */
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->spr[SPR_BOOKE_ESR] = 0x00000000;
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x10000000;
+ }
+ cs->exception_index = POWERPC_EXCP_ISI;
+ break;
+ case -4:
+ /* Direct store exception */
+ /* No code fetch is allowed in direct-store areas */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x10000000;
+ }
+ break;
+ }
+ } else {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ if (access_type == MMU_DATA_STORE) {
+ cs->exception_index = POWERPC_EXCP_DSTLB;
+ env->error_code = 1 << 16;
} else {
- env->error_code = 0x10000000;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
+ env->error_code = 0;
}
- cs->exception_index = POWERPC_EXCP_ISI;
+ env->spr[SPR_DMISS] = eaddr;
+ env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
+ tlb_miss:
+ env->error_code |= ctx.key << 19;
+ env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
+ get_pteg_offset32(cpu, ctx.hash[0]);
+ env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
+ get_pteg_offset32(cpu, ctx.hash[1]);
break;
- case -4:
- /* Direct store exception */
- /* No code fetch is allowed in direct-store areas */
- cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
+ case POWERPC_MMU_SOFT_4xx:
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->error_code = 0;
+ env->spr[SPR_40x_DEAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_40x_ESR] = 0x00800000;
} else {
- env->error_code = 0x10000000;
+ env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
- }
- } else {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_6xx:
- if (access_type == MMU_DATA_STORE) {
- cs->exception_index = POWERPC_EXCP_DSTLB;
- env->error_code = 1 << 16;
- } else {
- cs->exception_index = POWERPC_EXCP_DLTLB;
- env->error_code = 0;
- }
- env->spr[SPR_DMISS] = eaddr;
- env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
- tlb_miss:
- env->error_code |= ctx.key << 19;
- env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
- get_pteg_offset32(cpu, ctx.hash[0]);
- env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
- get_pteg_offset32(cpu, ctx.hash[1]);
- break;
- case POWERPC_MMU_SOFT_4xx:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] = 0x00800000;
- } else {
- env->spr[SPR_40x_ESR] = 0x00000000;
- }
- break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(cs, "PowerPC in real mode should never raise "
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case POWERPC_MMU_REAL:
+ cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
- default:
- cpu_abort(cs, "Unknown or invalid MMU model\n");
+ default:
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
+ env->spr[SPR_40x_DEAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_40x_ESR] |= 0x00800000;
}
+ } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ } else {
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x0A000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x08000000;
+ }
+ }
+ break;
+ case -4:
+ /* Direct store exception */
+ switch (type) {
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ cs->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
+ env->spr[SPR_DAR] = eaddr;
break;
- case -2:
- /* Access rights violation */
+ case ACCESS_RES:
+ /* lwarx, ldarx or stwcx. */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
- if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] |= 0x00800000;
- }
- } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06000000;
} else {
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x0A000000;
- } else {
- env->spr[SPR_DSISR] = 0x08000000;
- }
+ env->spr[SPR_DSISR] = 0x04000000;
}
break;
- case -4:
- /* Direct store exception */
- switch (type) {
- case ACCESS_FLOAT:
- /* Floating point load/store */
- cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = POWERPC_EXCP_ALIGN_FP;
- env->spr[SPR_DAR] = eaddr;
- break;
- case ACCESS_RES:
- /* lwarx, ldarx or stwcx. */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06000000;
- } else {
- env->spr[SPR_DSISR] = 0x04000000;
- }
- break;
- case ACCESS_EXT:
- /* eciwx or ecowx */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06100000;
- } else {
- env->spr[SPR_DSISR] = 0x04100000;
- }
- break;
- default:
- printf("DSI: invalid exception (%d)\n", ret);
- cs->exception_index = POWERPC_EXCP_PROGRAM;
- env->error_code =
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
- env->spr[SPR_DAR] = eaddr;
- break;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
}
break;
+ default:
+ printf("DSI: invalid exception (%d)\n", ret);
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+ env->spr[SPR_DAR] = eaddr;
+ break;
}
+ break;
}
}
return false;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (17 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:11 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
` (9 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
The "2" in booke206_update_mas_tlb_miss() call corresponds to
MMU_INST_FETCH which is the value of access_type in this branch;
mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
code access so using MMU_DATA_LOAD here seems wrong so replace it with
access_type here as well that yields the same result. This also makes
these calls the same as the data access branch further down.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 2487b4deff..762b13805b 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1288,13 +1288,13 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_40x_ESR] = 0x00000000;
break;
case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
/* fall through */
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
break;
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (18 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:47 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
` (8 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This function is not used from any other files so make it static and
fix the maybe used uninitialised warnings this has uncovered.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/internal.h | 5 +----
target/ppc/mmu_common.c | 5 ++++-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 601c0b533f..7a99f08dc8 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -261,10 +261,7 @@ typedef struct mmu_ctx_t mmu_ctx_t;
bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible);
-int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr,
- MMUAccessType access_type, int type,
- int mmu_idx);
+
/* Software driven TLB helpers */
int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
int way, int is_code);
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 762b13805b..4852cb5571 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -666,6 +666,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
hwaddr raddr = (hwaddr)-1ULL;
int i, ret = -1;
+ ctx->prot = 0;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
@@ -873,6 +874,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
hwaddr raddr = (hwaddr)-1ULL;
int i, j, ways, ret = -1;
+ ctx->prot = 0;
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
ways = booke206_tlb_ways(env, i);
for (j = 0; j < ways; j++) {
@@ -1144,7 +1146,7 @@ void dump_mmu(CPUPPCState *env)
}
}
-int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
+static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr,
MMUAccessType access_type, int type,
int mmu_idx)
@@ -1163,6 +1165,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
env->mmu_model == POWERPC_MMU_SOFT_4xx ||
env->mmu_model == POWERPC_MMU_REAL)) {
+ memset(ctx, 0, sizeof(*ctx));
ctx->raddr = eaddr;
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (19 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 10:49 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
` (7 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This type is only used within mmu_common.c. Move its definition from
internal.h to there.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/internal.h | 12 ------------
target/ppc/mmu_common.c | 11 +++++++++++
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 7a99f08dc8..61c2aadd0d 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -256,8 +256,6 @@ static inline int prot_for_access_type(MMUAccessType access_type)
/* PowerPC MMU emulation */
-typedef struct mmu_ctx_t mmu_ctx_t;
-
bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible);
@@ -265,16 +263,6 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
/* Software driven TLB helpers */
int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
int way, int is_code);
-/* Context used internally during MMU translations */
-struct mmu_ctx_t {
- hwaddr raddr; /* Real address */
- hwaddr eaddr; /* Effective address */
- int prot; /* Protection bits */
- hwaddr hash[2]; /* Pagetable hash values */
- target_ulong ptem; /* Virtual segment ID | API */
- int key; /* Access key */
- int nx; /* Non-execute area */
-};
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 4852cb5571..41ef174ab4 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -35,6 +35,17 @@
/* #define DUMP_PAGE_TABLES */
+/* Context used internally during MMU translations */
+typedef struct {
+ hwaddr raddr; /* Real address */
+ hwaddr eaddr; /* Effective address */
+ int prot; /* Protection bits */
+ hwaddr hash[2]; /* Pagetable hash values */
+ target_ulong ptem; /* Virtual segment ID | API */
+ int key; /* Access key */
+ int nx; /* Non-execute area */
+} mmu_ctx_t;
+
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
PowerPCCPU *cpu = env_archcpu(env);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (20 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 11:35 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
` (6 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
pp_check() in mmu_common.c. Rename the latter to ppc_pte_prot() and
merge with ppc_hash32_pp_prot() to remove duplicated code.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/internal.h | 2 +-
target/ppc/mmu-hash32.c | 47 +----------------------------------------
target/ppc/mmu_common.c | 19 +++++++++--------
3 files changed, 12 insertions(+), 56 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 61c2aadd0d..d7c923b017 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -255,7 +255,7 @@ static inline int prot_for_access_type(MMUAccessType access_type)
#ifndef CONFIG_USER_ONLY
/* PowerPC MMU emulation */
-
+int ppc_pte_prot(int key, int pp, int nx);
bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
int mmu_idx, bool guest_visible);
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 3976416840..ee9df351ae 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -42,51 +42,6 @@ struct mmu_ctx_hash32 {
int key; /* Access key */
};
-static int ppc_hash32_pp_prot(int key, int pp, int nx)
-{
- int prot;
-
- if (key == 0) {
- switch (pp) {
- case 0x0:
- case 0x1:
- case 0x2:
- prot = PAGE_READ | PAGE_WRITE;
- break;
-
- case 0x3:
- prot = PAGE_READ;
- break;
-
- default:
- abort();
- }
- } else {
- switch (pp) {
- case 0x0:
- prot = 0;
- break;
-
- case 0x1:
- case 0x3:
- prot = PAGE_READ;
- break;
-
- case 0x2:
- prot = PAGE_READ | PAGE_WRITE;
- break;
-
- default:
- abort();
- }
- }
- if (nx == 0) {
- prot |= PAGE_EXEC;
- }
-
- return prot;
-}
-
static int ppc_hash32_pte_prot(int mmu_idx,
target_ulong sr, ppc_hash_pte32_t pte)
{
@@ -95,7 +50,7 @@ static int ppc_hash32_pte_prot(int mmu_idx,
key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS));
pp = pte.pte1 & HPTE32_R_PP;
- return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
+ return ppc_pte_prot(key, pp, !!(sr & SR32_NX));
}
static target_ulong hash32_bat_size(int mmu_idx,
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 41ef174ab4..0ce5c1e841 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -75,22 +75,23 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
/*****************************************************************************/
/* PowerPC MMU emulation */
-static int pp_check(int key, int pp, int nx)
+int ppc_pte_prot(int key, int pp, int nx)
{
int access;
/* Compute access rights */
- access = 0;
if (key == 0) {
switch (pp) {
case 0x0:
case 0x1:
case 0x2:
- access |= PAGE_WRITE;
- /* fall through */
+ access = PAGE_READ | PAGE_WRITE;
+ break;
case 0x3:
- access |= PAGE_READ;
+ access = PAGE_READ;
break;
+ default:
+ g_assert_not_reached();
}
} else {
switch (pp) {
@@ -104,6 +105,8 @@ static int pp_check(int key, int pp, int nx)
case 0x2:
access = PAGE_READ | PAGE_WRITE;
break;
+ default:
+ g_assert_not_reached();
}
}
if (nx == 0) {
@@ -140,7 +143,7 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
MMUAccessType access_type)
{
target_ulong ptem, mmask;
- int access, ret, pteh, ptev, pp;
+ int ret, pteh, ptev, pp;
ret = -1;
/* Check validity and table match */
@@ -159,11 +162,9 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
return -3;
}
}
- /* Compute access rights */
- access = pp_check(ctx->key, pp, ctx->nx);
/* Keep the matching PTE information */
ctx->raddr = pte1;
- ctx->prot = access;
+ ctx->prot = ppc_pte_prot(ctx->key, pp, ctx->nx);
ret = check_prot(ctx->prot, access_type);
if (ret == 0) {
/* Access granted */
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (21 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 11:51 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
` (5 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 180 ++++++++++++++++++++++++++++++----------
1 file changed, 138 insertions(+), 42 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 0ce5c1e841..a1f98f8de4 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1250,6 +1250,137 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
}
+static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
+ MMUAccessType access_type,
+ hwaddr *raddrp, int *psizep, int *protp,
+ int mmu_idx, bool guest_visible)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ mmu_ctx_t ctx;
+ int ret;
+
+ if (env->mmu_model == POWERPC_MMU_BOOKE206) {
+ ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
+ mmu_idx);
+ } else {
+ ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
+ }
+ if (ret == 0) {
+ *raddrp = ctx.raddr;
+ *protp = ctx.prot;
+ *psizep = TARGET_PAGE_BITS;
+ return true;
+ } else if (!guest_visible) {
+ return false;
+ }
+
+ log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+ if (access_type == MMU_INST_FETCH) {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0;
+ break;
+ case -3:
+ /* No execute protection violation */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ env->spr[SPR_BOOKE_ESR] = 0;
+ env->error_code = 0;
+ break;
+ case -4:
+ /* Direct store exception */
+ /* No code fetch is allowed in direct-store areas */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0;
+ break;
+ }
+ } else {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case -4:
+ /* Direct store exception */
+ switch (env->access_type) {
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ cs->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
+ env->spr[SPR_DAR] = eaddr;
+ break;
+ case ACCESS_RES:
+ /* lwarx, ldarx or stwcx. */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04000000;
+ }
+ break;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
+ }
+ break;
+ default:
+ printf("DSI: invalid exception (%d)\n", ret);
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+ env->spr[SPR_DAR] = eaddr;
+ break;
+ }
+ break;
+ }
+ }
+ return false;
+}
+
/* Perform address translation */
/* TODO: Split this by mmu_model. */
static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
@@ -1302,15 +1433,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_40x_DEAR] = eaddr;
env->spr[SPR_40x_ESR] = 0x00000000;
break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
@@ -1321,34 +1443,18 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
case -2:
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
- } else {
- env->error_code = 0x08000000;
- }
+ env->error_code = 0x08000000;
break;
case -3:
/* No execute protection violation */
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_ESR] = 0x00000000;
- env->error_code = 0;
- } else {
- env->error_code = 0x10000000;
- }
cs->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x10000000;
break;
case -4:
/* Direct store exception */
/* No code fetch is allowed in direct-store areas */
cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
- } else {
- env->error_code = 0x10000000;
- }
+ env->error_code = 0x10000000;
break;
}
} else {
@@ -1383,15 +1489,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
case POWERPC_MMU_REAL:
cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
@@ -1408,10 +1505,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_40x_ESR] |= 0x00800000;
}
- } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
} else {
env->spr[SPR_DAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
@@ -1490,7 +1583,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
case POWERPC_MMU_32B:
return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
-
+ case POWERPC_MMU_BOOKE:
+ case POWERPC_MMU_BOOKE206:
+ return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
+ psizep, protp, mmu_idx, guest_visible);
default:
return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (22 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 12:05 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
` (4 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This function is no longer called for BookE MMU model so remove parts
related to it. This has uncovered a few may be used uninitialised
warnings that are also fixed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 25 +++++--------------------
1 file changed, 5 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index a1f98f8de4..d61c41d8c9 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -684,12 +684,10 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
access_type, i);
if (ret != -1) {
- if (ret >= 0) {
- ctx->raddr = raddr;
- }
break;
}
}
+ ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU,
"%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
" %d %d\n", __func__, ret < 0 ? "refused" : "granted",
@@ -897,9 +895,6 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
access_type, mmu_idx);
if (ret != -1) {
- if (ret >= 0) {
- ctx->raddr = raddr;
- }
goto found_tlb;
}
}
@@ -907,6 +902,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
found_tlb:
+ ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
HWADDR_FMT_plx " %d %d\n", __func__,
ret < 0 ? "refused" : "granted", address, raddr,
@@ -1163,20 +1159,9 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
MMUAccessType access_type, int type,
int mmu_idx)
{
- bool real_mode;
-
- if (env->mmu_model == POWERPC_MMU_BOOKE) {
- return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
- } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
- return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
- mmu_idx);
- }
-
- real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
- : !FIELD_EX64(env->msr, MSR, DR);
- if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
- env->mmu_model == POWERPC_MMU_SOFT_4xx ||
- env->mmu_model == POWERPC_MMU_REAL)) {
+ bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
+ : !FIELD_EX64(env->msr, MSR, DR);
+ if (real_mode) {
memset(ctx, 0, sizeof(*ctx));
ctx->raddr = eaddr;
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate()
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (23 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 12:15 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
` (3 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 147 +++++++++++++++-------------------------
1 file changed, 56 insertions(+), 91 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index d61c41d8c9..b76611da80 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1261,106 +1261,71 @@ static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
}
log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+ env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ }
if (access_type == MMU_INST_FETCH) {
- switch (ret) {
- case -1:
+ if (ret == -1) {
/* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- default:
- g_assert_not_reached();
- }
- break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0;
- break;
- case -3:
- /* No execute protection violation */
- cs->exception_index = POWERPC_EXCP_ISI;
- env->spr[SPR_BOOKE_ESR] = 0;
- env->error_code = 0;
- break;
- case -4:
- /* Direct store exception */
- /* No code fetch is allowed in direct-store areas */
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ } else {
cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0;
- break;
- }
- } else {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- default:
- g_assert_not_reached();
+ if (ret == -3) {
+ /* No execute protection violation */
+ env->spr[SPR_BOOKE_ESR] = 0;
}
+ }
+ return false;
+ }
+
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case -4:
+ /* Direct store exception */
+ env->spr[SPR_DAR] = eaddr;
+ switch (env->access_type) {
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ cs->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
break;
- case -2:
- /* Access rights violation */
+ case ACCESS_RES:
+ /* lwarx, ldarx or stwcx. */
cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04000000;
+ }
break;
- case -4:
- /* Direct store exception */
- switch (env->access_type) {
- case ACCESS_FLOAT:
- /* Floating point load/store */
- cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = POWERPC_EXCP_ALIGN_FP;
- env->spr[SPR_DAR] = eaddr;
- break;
- case ACCESS_RES:
- /* lwarx, ldarx or stwcx. */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06000000;
- } else {
- env->spr[SPR_DSISR] = 0x04000000;
- }
- break;
- case ACCESS_EXT:
- /* eciwx or ecowx */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06100000;
- } else {
- env->spr[SPR_DSISR] = 0x04100000;
- }
- break;
- default:
- printf("DSI: invalid exception (%d)\n", ret);
- cs->exception_index = POWERPC_EXCP_PROGRAM;
- env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
- env->spr[SPR_DAR] = eaddr;
- break;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
}
break;
+ default:
+ printf("DSI: invalid exception (%d)\n", ret);
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+ break;
}
}
return false;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (24 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 12:17 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
` (2 subsequent siblings)
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 300 ++++++++++++++++++++--------------------
1 file changed, 150 insertions(+), 150 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index b76611da80..204b8af455 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -910,6 +910,156 @@ found_tlb:
return ret;
}
+static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
+ MMUAccessType access_type, int mmu_idx)
+{
+ uint32_t epid;
+ bool as, pr;
+ uint32_t missed_tid = 0;
+ bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
+
+ if (access_type == MMU_INST_FETCH) {
+ as = FIELD_EX64(env->msr, MSR, IR);
+ }
+ env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
+ env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
+ env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
+ env->spr[SPR_BOOKE_MAS3] = 0;
+ env->spr[SPR_BOOKE_MAS6] = 0;
+ env->spr[SPR_BOOKE_MAS7] = 0;
+
+ /* AS */
+ if (as) {
+ env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
+ env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
+ }
+
+ env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
+ env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
+
+ if (!use_epid) {
+ switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
+ case MAS4_TIDSELD_PID0:
+ missed_tid = env->spr[SPR_BOOKE_PID];
+ break;
+ case MAS4_TIDSELD_PID1:
+ missed_tid = env->spr[SPR_BOOKE_PID1];
+ break;
+ case MAS4_TIDSELD_PID2:
+ missed_tid = env->spr[SPR_BOOKE_PID2];
+ break;
+ }
+ env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
+ } else {
+ missed_tid = epid;
+ env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
+ }
+ env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
+
+
+ /* next victim logic */
+ env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
+ env->last_way++;
+ env->last_way &= booke206_tlb_ways(env, 0) - 1;
+ env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
+}
+
+static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
+ MMUAccessType access_type,
+ hwaddr *raddrp, int *psizep, int *protp,
+ int mmu_idx, bool guest_visible)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ mmu_ctx_t ctx;
+ int ret;
+
+ if (env->mmu_model == POWERPC_MMU_BOOKE206) {
+ ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
+ mmu_idx);
+ } else {
+ ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
+ }
+ if (ret == 0) {
+ *raddrp = ctx.raddr;
+ *protp = ctx.prot;
+ *psizep = TARGET_PAGE_BITS;
+ return true;
+ } else if (!guest_visible) {
+ return false;
+ }
+
+ log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+ env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ }
+ if (access_type == MMU_INST_FETCH) {
+ if (ret == -1) {
+ /* No matches in page tables or TLB */
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ } else {
+ cs->exception_index = POWERPC_EXCP_ISI;
+ if (ret == -3) {
+ /* No execute protection violation */
+ env->spr[SPR_BOOKE_ESR] = 0;
+ }
+ }
+ return false;
+ }
+
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case -4:
+ /* Direct store exception */
+ env->spr[SPR_DAR] = eaddr;
+ switch (env->access_type) {
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ cs->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
+ break;
+ case ACCESS_RES:
+ /* lwarx, ldarx or stwcx. */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04000000;
+ }
+ break;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
+ }
+ break;
+ default:
+ printf("DSI: invalid exception (%d)\n", ret);
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+ break;
+ }
+ }
+ return false;
+}
+
static const char *book3e_tsize_to_str[32] = {
"1K", "2K", "4K", "8K", "16K", "32K", "64K", "128K", "256K", "512K",
"1M", "2M", "4M", "8M", "16M", "32M", "64M", "128M", "256M", "512M",
@@ -1181,156 +1331,6 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
}
}
-static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
- MMUAccessType access_type, int mmu_idx)
-{
- uint32_t epid;
- bool as, pr;
- uint32_t missed_tid = 0;
- bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
-
- if (access_type == MMU_INST_FETCH) {
- as = FIELD_EX64(env->msr, MSR, IR);
- }
- env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
- env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
- env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
- env->spr[SPR_BOOKE_MAS3] = 0;
- env->spr[SPR_BOOKE_MAS6] = 0;
- env->spr[SPR_BOOKE_MAS7] = 0;
-
- /* AS */
- if (as) {
- env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
- env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
- }
-
- env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
- env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
-
- if (!use_epid) {
- switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
- case MAS4_TIDSELD_PID0:
- missed_tid = env->spr[SPR_BOOKE_PID];
- break;
- case MAS4_TIDSELD_PID1:
- missed_tid = env->spr[SPR_BOOKE_PID1];
- break;
- case MAS4_TIDSELD_PID2:
- missed_tid = env->spr[SPR_BOOKE_PID2];
- break;
- }
- env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
- } else {
- missed_tid = epid;
- env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
- }
- env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
-
-
- /* next victim logic */
- env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
- env->last_way++;
- env->last_way &= booke206_tlb_ways(env, 0) - 1;
- env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
-}
-
-static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
- MMUAccessType access_type,
- hwaddr *raddrp, int *psizep, int *protp,
- int mmu_idx, bool guest_visible)
-{
- CPUState *cs = CPU(cpu);
- CPUPPCState *env = &cpu->env;
- mmu_ctx_t ctx;
- int ret;
-
- if (env->mmu_model == POWERPC_MMU_BOOKE206) {
- ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
- mmu_idx);
- } else {
- ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
- }
- if (ret == 0) {
- *raddrp = ctx.raddr;
- *protp = ctx.prot;
- *psizep = TARGET_PAGE_BITS;
- return true;
- } else if (!guest_visible) {
- return false;
- }
-
- log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
- env->error_code = 0;
- if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- }
- if (access_type == MMU_INST_FETCH) {
- if (ret == -1) {
- /* No matches in page tables or TLB */
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- } else {
- cs->exception_index = POWERPC_EXCP_ISI;
- if (ret == -3) {
- /* No execute protection violation */
- env->spr[SPR_BOOKE_ESR] = 0;
- }
- }
- return false;
- }
-
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- case -4:
- /* Direct store exception */
- env->spr[SPR_DAR] = eaddr;
- switch (env->access_type) {
- case ACCESS_FLOAT:
- /* Floating point load/store */
- cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = POWERPC_EXCP_ALIGN_FP;
- break;
- case ACCESS_RES:
- /* lwarx, ldarx or stwcx. */
- cs->exception_index = POWERPC_EXCP_DSI;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06000000;
- } else {
- env->spr[SPR_DSISR] = 0x04000000;
- }
- break;
- case ACCESS_EXT:
- /* eciwx or ecowx */
- cs->exception_index = POWERPC_EXCP_DSI;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06100000;
- } else {
- env->spr[SPR_DSISR] = 0x04100000;
- }
- break;
- default:
- printf("DSI: invalid exception (%d)\n", ret);
- cs->exception_index = POWERPC_EXCP_PROGRAM;
- env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
- break;
- }
- }
- return false;
-}
-
/* Perform address translation */
/* TODO: Split this by mmu_model. */
static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (25 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 12:30 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/pegasos2.c | 2 +-
target/ppc/cpu.h | 1 -
target/ppc/cpu_init.c | 19 +++++--------------
target/ppc/helper_regs.c | 1 -
target/ppc/mmu_common.c | 10 ++--------
target/ppc/mmu_helper.c | 12 ++----------
6 files changed, 10 insertions(+), 35 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 04d6decb2b..dfc6fab180 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -984,7 +984,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
cpu->env.icache_line_size);
qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
cpu->env.icache_line_size);
- if (cpu->env.id_tlbs) {
+ if (cpu->env.tlb_type == TLB_6XX) {
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0ac55d6b25..21e12a4f0d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1260,7 +1260,6 @@ struct CPUArchState {
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
int nb_ways; /* Number of ways in the TLB set */
int last_way; /* Last used way used to allocate TLB in a LRU way */
- int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
int nb_pids; /* Number of available PID registers */
int tlb_type; /* Type of TLB we're dealing with */
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c11a69fd90..07ad788e54 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2117,7 +2117,6 @@ static void init_proc_405(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
- env->id_tlbs = 0;
env->tlb_type = TLB_EMB;
#endif
init_excp_4xx(env);
@@ -2190,7 +2189,6 @@ static void init_proc_440EP(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
- env->id_tlbs = 0;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
@@ -2288,7 +2286,6 @@ static void init_proc_440GP(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
- env->id_tlbs = 0;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
@@ -2362,7 +2359,6 @@ static void init_proc_440x5(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
- env->id_tlbs = 0;
env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
@@ -2724,7 +2720,6 @@ static void init_proc_e200(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
- env->id_tlbs = 0;
env->tlb_type = TLB_EMB;
#endif
init_excp_e200(env, 0xFFFF0000UL);
@@ -2843,7 +2838,6 @@ static void init_proc_e500(CPUPPCState *env, int version)
/* Memory management */
env->nb_pids = 3;
env->nb_ways = 2;
- env->id_tlbs = 0;
switch (version) {
case fsl_e500v1:
tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
@@ -6800,20 +6794,17 @@ static void init_ppc_proc(PowerPCCPU *cpu)
}
/* Allocate TLBs buffer when needed */
#if !defined(CONFIG_USER_ONLY)
- if (env->nb_tlb != 0) {
- int nb_tlb = env->nb_tlb;
- if (env->id_tlbs != 0) {
- nb_tlb *= 2;
- }
+ if (env->nb_tlb) {
switch (env->tlb_type) {
case TLB_6XX:
- env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
+ /* 6xx has separate TLBs for instructions and data hence times 2 */
+ env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
break;
case TLB_EMB:
- env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
+ env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
break;
case TLB_MAS:
- env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
+ env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
break;
}
/* Pre-compute some useful values */
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 25258986e3..ed583fe9b3 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -693,7 +693,6 @@ void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
env->nb_ways = nb_ways;
- env->id_tlbs = 1;
env->tlb_type = TLB_6XX;
spr_register(env, SPR_DMISS, "DMISS",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 204b8af455..a0b34f9637 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -130,8 +130,8 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
/* Select TLB way */
nr += env->tlb_per_way * way;
- /* 6xx have separate TLBs for instructions and data */
- if (is_code && env->id_tlbs == 1) {
+ /* 6xx has separate TLBs for instructions and data */
+ if (is_code) {
nr += env->nb_tlb;
}
@@ -1246,13 +1246,7 @@ static void mmu6xx_dump_mmu(CPUPPCState *env)
mmu6xx_dump_BATs(env, ACCESS_INT);
mmu6xx_dump_BATs(env, ACCESS_CODE);
- if (env->id_tlbs != 1) {
- qemu_printf("ERROR: 6xx MMU should have separated TLB"
- " for code and data\n");
- }
-
qemu_printf("\nTLBs [EPN EPN + SIZE]\n");
-
for (type = 0; type < 2; type++) {
for (way = 0; way < env->nb_ways; way++) {
for (entry = env->nb_tlb * type + env->tlb_per_way * way;
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 817836b731..87c611888b 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -44,14 +44,8 @@
static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
{
ppc6xx_tlb_t *tlb;
- int nr, max;
+ int nr, max = 2 * env->nb_tlb;
- /* LOG_SWTLB("Invalidate all TLBs\n"); */
- /* Invalidate all defined software TLB */
- max = env->nb_tlb;
- if (env->id_tlbs == 1) {
- max *= 2;
- }
for (nr = 0; nr < max; nr++) {
tlb = &env->tlb.tlb6[nr];
pte_invalidate(&tlb->pte0);
@@ -307,9 +301,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
ppc6xx_tlb_invalidate_virt(env, addr, 0);
- if (env->id_tlbs == 1) {
- ppc6xx_tlb_invalidate_virt(env, addr, 1);
- }
+ ppc6xx_tlb_invalidate_virt(env, addr, 1);
break;
case POWERPC_MMU_32B:
/*
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (26 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
@ 2024-05-01 23:43 ` BALATON Zoltan
2024-05-07 12:40 ` Nicholas Piggin
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
28 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-01 23:43 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza
Several 4xx related CPUs have the same TLB settings. Split it off in a
common function in cpu_init.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/cpu_init.c | 46 ++++++++++++++++---------------------------
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 07ad788e54..d7e85c1b07 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2107,18 +2107,22 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
return 0;
}
+static void init_tlbs_4xx(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->tlb_type = TLB_EMB;
+#endif
+}
+
static void init_proc_405(CPUPPCState *env)
{
register_40x_sprs(env);
register_405_sprs(env);
register_usprgh_sprs(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->tlb_type = TLB_EMB;
-#endif
+ init_tlbs_4xx(env);
init_excp_4xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2185,12 +2189,8 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->tlb_type = TLB_EMB;
-#endif
+
+ init_tlbs_4xx(env);
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2282,12 +2282,7 @@ static void init_proc_440GP(CPUPPCState *env)
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->tlb_type = TLB_EMB;
-#endif
+ init_tlbs_4xx(env);
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2355,12 +2350,8 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->tlb_type = TLB_EMB;
-#endif
+
+ init_tlbs_4xx(env);
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2717,11 +2708,8 @@ static void init_proc_e200(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->tlb_type = TLB_EMB;
-#endif
+
+ init_tlbs_4xx(env);
init_excp_e200(env, 0xFFFF0000UL);
env->dcache_line_size = 32;
env->icache_line_size = 32;
--
2.30.9
^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [PATCH v2 04/28] target/ppc: Remove unused helper
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
@ 2024-05-07 9:18 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:18 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The helper_rac function is defined but not used, remove it.
>
> Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviwed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/helper.h | 2 --
> target/ppc/mmu_helper.c | 24 ------------------------
> 2 files changed, 26 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 86f97ee1e7..f769e01c3d 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -700,8 +700,6 @@ DEF_HELPER_2(book3s_msgclr, void, env, tl)
>
> DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32)
> #if !defined(CONFIG_USER_ONLY)
> -DEF_HELPER_2(rac, tl, env, tl)
> -
> DEF_HELPER_2(load_dcr, tl, env, tl)
> DEF_HELPER_3(store_dcr, void, env, tl, tl)
> #endif
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index c071b4d5e2..817836b731 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -595,30 +595,6 @@ void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN)
> do_6xx_tlb(env, EPN, 1);
> }
>
> -/*****************************************************************************/
> -/* PowerPC 601 specific instructions (POWER bridge) */
> -
> -target_ulong helper_rac(CPUPPCState *env, target_ulong addr)
> -{
> - mmu_ctx_t ctx;
> - int nb_BATs;
> - target_ulong ret = 0;
> -
> - /*
> - * We don't have to generate many instances of this instruction,
> - * as rac is supervisor only.
> - *
> - * XXX: FIX THIS: Pretend we have no BAT
> - */
> - nb_BATs = env->nb_BATs;
> - env->nb_BATs = 0;
> - if (get_physical_address_wtlb(env, &ctx, addr, 0, ACCESS_INT, 0) == 0) {
> - ret = ctx.raddr;
> - }
> - env->nb_BATs = nb_BATs;
> - return ret;
> -}
> -
> static inline target_ulong booke_tlb_to_page_size(int size)
> {
> return 1024 << (2 * size);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
@ 2024-05-07 9:19 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:19 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> In mmubooke_check_tlb() prot2 is calculated first but only used after
> an unrelated check that can return before tha value is used. Move the
> calculation after the check, closer to where it is used, to keep them
> together and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviwed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/mmu_common.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 751403f1c8..168ff842a5 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -634,12 +634,6 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
> return -1;
> }
>
> - if (FIELD_EX64(env->msr, MSR, PR)) {
> - prot2 = tlb->prot & 0xF;
> - } else {
> - prot2 = (tlb->prot >> 4) & 0xF;
> - }
> -
> /* Check the address space */
> if ((access_type == MMU_INST_FETCH ?
> FIELD_EX64(env->msr, MSR, IR) :
> @@ -648,6 +642,11 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
> return -1;
> }
>
> + if (FIELD_EX64(env->msr, MSR, PR)) {
> + prot2 = tlb->prot & 0xF;
> + } else {
> + prot2 = (tlb->prot >> 4) & 0xF;
> + }
> *prot = prot2;
> if (prot2 & prot_for_access_type(access_type)) {
> qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 06/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
@ 2024-05-07 9:20 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:20 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> In mmubooke206_check_tlb() prot2 is calculated first but only used
> after an unrelated check that can return before tha value is used.
> Move the calculation after the check, closer to where it is used, to
> keep them together and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviwed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/mmu_common.c | 25 ++++++++++++-------------
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 168ff842a5..b0aca8ec02 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -828,6 +828,18 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
>
> found_tlb:
>
> + /* Check the address space and permissions */
> + if (access_type == MMU_INST_FETCH) {
> + /* There is no way to fetch code using epid load */
> + assert(!use_epid);
> + as = FIELD_EX64(env->msr, MSR, IR);
> + }
> +
> + if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
> + qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
> + return -1;
> + }
> +
> if (pr) {
> if (tlb->mas7_3 & MAS3_UR) {
> prot2 |= PAGE_READ;
> @@ -849,19 +861,6 @@ found_tlb:
> prot2 |= PAGE_EXEC;
> }
> }
> -
> - /* Check the address space and permissions */
> - if (access_type == MMU_INST_FETCH) {
> - /* There is no way to fetch code using epid load */
> - assert(!use_epid);
> - as = FIELD_EX64(env->msr, MSR, IR);
> - }
> -
> - if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
> - qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
> - return -1;
> - }
> -
> *prot = prot2;
> if (prot2 & prot_for_access_type(access_type)) {
> qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
@ 2024-05-07 9:30 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:30 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
> value directly the the destination, no need to have a separate local
> variable for it.
>
For a minute I thought this changed the interface to now update
ctx->prot even if the lookup failed, but it already does that in
some cases so... no issue.
If this was more widely used API we'd rather change it to never
update *prot on failure, but okay we can do this.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 30 +++++++++++++-----------------
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index b0aca8ec02..74c3b814c9 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -627,8 +627,6 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
> hwaddr *raddr, int *prot, target_ulong address,
> MMUAccessType access_type, int i)
> {
> - int prot2;
> -
> if (!mmubooke_check_pid(env, tlb, raddr, address, i)) {
> qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__);
> return -1;
> @@ -643,17 +641,16 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
> }
>
> if (FIELD_EX64(env->msr, MSR, PR)) {
> - prot2 = tlb->prot & 0xF;
> + *prot = tlb->prot & 0xF;
> } else {
> - prot2 = (tlb->prot >> 4) & 0xF;
> + *prot = (tlb->prot >> 4) & 0xF;
> }
> - *prot = prot2;
> - if (prot2 & prot_for_access_type(access_type)) {
> + if (*prot & prot_for_access_type(access_type)) {
> qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
> return 0;
> }
>
> - qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
> + qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot);
> return access_type == MMU_INST_FETCH ? -3 : -2;
> }
>
> @@ -794,7 +791,6 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
> target_ulong address,
> MMUAccessType access_type, int mmu_idx)
> {
> - int prot2 = 0;
> uint32_t epid;
> bool as, pr;
> bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
> @@ -840,34 +836,34 @@ found_tlb:
> return -1;
> }
>
> + *prot = 0;
> if (pr) {
> if (tlb->mas7_3 & MAS3_UR) {
> - prot2 |= PAGE_READ;
> + *prot |= PAGE_READ;
> }
> if (tlb->mas7_3 & MAS3_UW) {
> - prot2 |= PAGE_WRITE;
> + *prot |= PAGE_WRITE;
> }
> if (tlb->mas7_3 & MAS3_UX) {
> - prot2 |= PAGE_EXEC;
> + *prot |= PAGE_EXEC;
> }
> } else {
> if (tlb->mas7_3 & MAS3_SR) {
> - prot2 |= PAGE_READ;
> + *prot |= PAGE_READ;
> }
> if (tlb->mas7_3 & MAS3_SW) {
> - prot2 |= PAGE_WRITE;
> + *prot |= PAGE_WRITE;
> }
> if (tlb->mas7_3 & MAS3_SX) {
> - prot2 |= PAGE_EXEC;
> + *prot |= PAGE_EXEC;
> }
> }
> - *prot = prot2;
> - if (prot2 & prot_for_access_type(access_type)) {
> + if (*prot & prot_for_access_type(access_type)) {
> qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
> return 0;
> }
>
> - qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
> + qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot);
> return access_type == MMU_INST_FETCH ? -3 : -2;
> }
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
@ 2024-05-07 9:34 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:34 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> In get_physical_address_wtlb() the real_mode flag depends on either
> the MSR[IR] or MSR[DR] bit depending on access_type. Extract just the
> needed bit in a more straight forward way instead of doing unnecessary
> computation.
Hopefully the compiler should be able to work it out, but IMO it
reads better with your change.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 74c3b814c9..45b6501ecb 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1183,8 +1183,10 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> int mmu_idx)
> {
> int ret = -1;
> - bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR)) ||
> - (type != ACCESS_CODE && !FIELD_EX64(env->msr, MSR, DR));
> + bool real_mode;
> +
> + real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> + : !FIELD_EX64(env->msr, MSR, DR);
>
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
@ 2024-05-07 9:36 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:36 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The default case will catch this and abort the same way and there is
> still a warning about it in ppc_tlb_invalidate_all() so drop these
> from mmu_common.c to simplify this code.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 45b6501ecb..98730035b1 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1218,10 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
> mmu_idx);
> break;
> - case POWERPC_MMU_MPC8xx:
> - /* XXX: TODO */
> - cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
> - break;
> case POWERPC_MMU_REAL:
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, access_type);
> @@ -1352,8 +1348,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_BOOKE_DEAR] = eaddr;
> env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
> break;
> - case POWERPC_MMU_MPC8xx:
> - cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> @@ -1426,9 +1420,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_ESR] = 0x00000000;
> }
> break;
> - case POWERPC_MMU_MPC8xx:
> - /* XXX: TODO */
> - cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> case POWERPC_MMU_BOOKE206:
> booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> /* fall through */
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
@ 2024-05-07 9:42 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:42 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Repurpose get_segment_6xx_tlb() to do the whole address translation
> for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
> renaming it to match other similar functions. These are only called
> once together so no need to keep these separate functions and
> combining them simplifies the caller allowing further restructuring.
Looks good...
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 98730035b1..ef1669b01d 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -359,19 +359,25 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
> return ret;
> }
>
> -/* Perform segment based translation */
> -static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
> - target_ulong eaddr, MMUAccessType access_type,
> - int type)
> +static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> + target_ulong eaddr,
> + MMUAccessType access_type, int type)
> {
> PowerPCCPU *cpu = env_archcpu(env);
> hwaddr hash;
> - target_ulong vsid;
> - int ds, target_page_bits;
> + target_ulong vsid, sr, pgidx;
> bool pr;
> - int ret;
> - target_ulong sr, pgidx;
> + int ds, target_page_bits, ret = -1;
>
> + /* First try to find a BAT entry if there are any */
> + if (env->nb_BATs != 0) {
> + ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
> + }
> + if (ret >= 0) {
> + return ret;
> + }
Would you consider not doing any rearranging of local variables there
and change this as:
/* First try to find a BAT entry if there are any */
if (env->nb_BATs != 0) {
int ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
if (ret >= 0) {
return ret;
}
}
Otherwise,
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> + /* Perform segment based translation when no BATs matched */
> pr = FIELD_EX64(env->msr, MSR, PR);
> ctx->eaddr = eaddr;
>
> @@ -1193,14 +1199,8 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, access_type);
> } else {
> - /* Try to find a BAT */
> - if (env->nb_BATs != 0) {
> - ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
> - }
> - if (ret < 0) {
> - /* We didn't match any BAT entry or don't have BATs */
> - ret = get_segment_6xx_tlb(env, ctx, eaddr, access_type, type);
> - }
> + ret = mmu6xx_get_physical_address(env, ctx, eaddr, access_type,
> + type);
> }
> break;
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb()
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
@ 2024-05-07 9:43 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:43 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Rename to ppc6xx_tlb_get_bat() to match other similar names in the
> same file.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/mmu_common.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index ef1669b01d..a069e4083f 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -288,8 +288,8 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
> *protp = prot;
> }
>
> -static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
> - target_ulong virtual, MMUAccessType access_type)
> +static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
> + target_ulong virtual, MMUAccessType access_type)
> {
> target_ulong *BATlt, *BATut, *BATu, *BATl;
> target_ulong BEPIl, BEPIu, bl;
> @@ -371,7 +371,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>
> /* First try to find a BAT entry if there are any */
> if (env->nb_BATs != 0) {
> - ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
> + ret = ppc6xx_tlb_get_bat(env, ctx, eaddr, access_type);
> }
> if (ret >= 0) {
> return ret;
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
@ 2024-05-07 9:50 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:50 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> BookE does not have real mode so split off and handle it first in
> get_physical_address_wtlb() before checking for real mode for other
> MMU models.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index a069e4083f..24a9b9ef19 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1191,6 +1191,13 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> int ret = -1;
> bool real_mode;
>
> + if (env->mmu_model == POWERPC_MMU_BOOKE) {
> + return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
> + } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> + return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
> + mmu_idx);
> + }
> +
> real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> : !FIELD_EX64(env->msr, MSR, DR);
>
> @@ -1211,13 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> ret = mmu40x_get_physical_address(env, ctx, eaddr, access_type);
> }
> break;
> - case POWERPC_MMU_BOOKE:
> - ret = mmubooke_get_physical_address(env, ctx, eaddr, access_type);
> - break;
> - case POWERPC_MMU_BOOKE206:
> - ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
> - mmu_idx);
> - break;
> case POWERPC_MMU_REAL:
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, access_type);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb()
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
@ 2024-05-07 9:58 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 9:58 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The real mode handling is identical in the remaining switch cases.
> Split off these common real mode cases into a separate conditional to
> leave only the else branches in the switch that are different.
>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 34 +++++++++-------------------------
> 1 file changed, 9 insertions(+), 25 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 24a9b9ef19..3132030baa 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1188,7 +1188,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> MMUAccessType access_type, int type,
> int mmu_idx)
> {
> - int ret = -1;
> bool real_mode;
>
> if (env->mmu_model == POWERPC_MMU_BOOKE) {
> @@ -1200,38 +1199,23 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>
> real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> : !FIELD_EX64(env->msr, MSR, DR);
> + if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> + env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> + env->mmu_model == POWERPC_MMU_REAL)) {
> + return check_physical(env, ctx, eaddr, access_type);
> + }
>
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> - if (real_mode) {
> - ret = check_physical(env, ctx, eaddr, access_type);
> - } else {
> - ret = mmu6xx_get_physical_address(env, ctx, eaddr, access_type,
> - type);
> - }
> - break;
> -
> + return mmu6xx_get_physical_address(env, ctx, eaddr, access_type, type);
> case POWERPC_MMU_SOFT_4xx:
> - if (real_mode) {
> - ret = check_physical(env, ctx, eaddr, access_type);
> - } else {
> - ret = mmu40x_get_physical_address(env, ctx, eaddr, access_type);
> - }
> - break;
> + return mmu40x_get_physical_address(env, ctx, eaddr, access_type);
> case POWERPC_MMU_REAL:
> - if (real_mode) {
> - ret = check_physical(env, ctx, eaddr, access_type);
> - } else {
> - cpu_abort(env_cpu(env),
> - "PowerPC in real mode do not do any translation\n");
> - }
> - return -1;
> + cpu_abort(env_cpu(env),
> + "PowerPC in real mode do not do any translation\n");
> default:
> cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n");
> - return -1;
> }
> -
> - return ret;
> }
>
> static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical()
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
@ 2024-05-07 10:00 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:00 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function just does two assignments and and unnecessary check that
> is always true so inline it in the only caller left and remove it.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 26 +++-----------------------
> 1 file changed, 3 insertions(+), 23 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 3132030baa..fab86a8f3e 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1161,28 +1161,6 @@ void dump_mmu(CPUPPCState *env)
> }
> }
>
> -static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
> - MMUAccessType access_type)
> -{
> - ctx->raddr = eaddr;
> - ctx->prot = PAGE_READ | PAGE_EXEC;
> -
> - switch (env->mmu_model) {
> - case POWERPC_MMU_SOFT_6xx:
> - case POWERPC_MMU_SOFT_4xx:
> - case POWERPC_MMU_REAL:
> - case POWERPC_MMU_BOOKE:
> - ctx->prot |= PAGE_WRITE;
> - break;
> -
> - default:
> - /* Caller's checks mean we should never get here for other models */
> - g_assert_not_reached();
> - }
> -
> - return 0;
> -}
> -
> int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> target_ulong eaddr,
> MMUAccessType access_type, int type,
> @@ -1202,7 +1180,9 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> env->mmu_model == POWERPC_MMU_REAL)) {
> - return check_physical(env, ctx, eaddr, access_type);
> + ctx->raddr = eaddr;
> + ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> + return 0;
> }
>
> switch (env->mmu_model) {
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address()
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
@ 2024-05-07 10:03 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:03 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/mmu_common.c | 25 +++++++++----------------
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index fab86a8f3e..760e4072b2 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -665,31 +665,24 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> MMUAccessType access_type)
> {
> ppcemb_tlb_t *tlb;
> - hwaddr raddr;
> - int i, ret;
> + hwaddr raddr = (hwaddr)-1ULL;
> + int i, ret = -1;
>
> - ret = -1;
> - raddr = (hwaddr)-1ULL;
> for (i = 0; i < env->nb_tlb; i++) {
> tlb = &env->tlb.tlbe[i];
> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> access_type, i);
> if (ret != -1) {
> + if (ret >= 0) {
> + ctx->raddr = raddr;
> + }
> break;
> }
> }
> -
> - if (ret >= 0) {
> - ctx->raddr = raddr;
> - qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
> - " => " HWADDR_FMT_plx " %d %d\n", __func__,
> - address, ctx->raddr, ctx->prot, ret);
> - } else {
> - qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
> - " => " HWADDR_FMT_plx " %d %d\n", __func__,
> - address, raddr, ctx->prot, ret);
> - }
> -
> + qemu_log_mask(CPU_LOG_MMU,
> + "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
> + " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
> + address, raddr, ctx->prot, ret);
> return ret;
> }
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address()
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
@ 2024-05-07 10:04 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:04 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is similar to mmubooke_get_physical_address() and can be
> simplified the same way.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 28 ++++++++++------------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 760e4072b2..ebf18a751c 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -872,15 +872,11 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> int mmu_idx)
> {
> ppcmas_tlb_t *tlb;
> - hwaddr raddr;
> - int i, j, ret;
> -
> - ret = -1;
> - raddr = (hwaddr)-1ULL;
> + hwaddr raddr = (hwaddr)-1ULL;
> + int i, j, ways, ret = -1;
>
> for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> - int ways = booke206_tlb_ways(env, i);
Don't need to bring the ways variable into a larger scope I think?
Otherwise,
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> -
> + ways = booke206_tlb_ways(env, i);
> for (j = 0; j < ways; j++) {
> tlb = booke206_get_tlbm(env, i, address, j);
> if (!tlb) {
> @@ -889,6 +885,9 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> access_type, mmu_idx);
> if (ret != -1) {
> + if (ret >= 0) {
> + ctx->raddr = raddr;
> + }
> goto found_tlb;
> }
> }
> @@ -896,17 +895,10 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>
> found_tlb:
>
> - if (ret >= 0) {
> - ctx->raddr = raddr;
> - qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
> - " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
> - ctx->raddr, ctx->prot, ret);
> - } else {
> - qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
> - " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
> - raddr, ctx->prot, ret);
> - }
> -
> + qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
> + HWADDR_FMT_plx " %d %d\n", __func__,
> + ret < 0 ? "refused" : "granted", address, raddr,
> + ctx->prot, ret);
> return ret;
> }
>
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
@ 2024-05-07 10:05 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:05 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Fix several qemu_log_mask() calls that are misindented.
Acked-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 42 ++++++++++++++++++++---------------------
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index ebf18a751c..28847c32f2 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -297,8 +297,8 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
> int ret = -1;
> bool ifetch = access_type == MMU_INST_FETCH;
>
> - qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
> - ifetch ? 'I' : 'D', virtual);
> + qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
> + ifetch ? 'I' : 'D', virtual);
> if (ifetch) {
> BATlt = env->IBAT[1];
> BATut = env->IBAT[0];
> @@ -312,9 +312,9 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
> BEPIu = *BATu & 0xF0000000;
> BEPIl = *BATu & 0x0FFE0000;
> bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
> - qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
> - TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
> - ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
> + qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
> + TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
> + ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
> if ((virtual & 0xF0000000) == BEPIu &&
> ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
> /* BAT matches */
> @@ -346,12 +346,11 @@ static int ppc6xx_tlb_get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
> BEPIu = *BATu & 0xF0000000;
> BEPIl = *BATu & 0x0FFE0000;
> bl = (*BATu & 0x00001FFC) << 15;
> - qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v "
> - TARGET_FMT_lx " BATu " TARGET_FMT_lx
> - " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
> - TARGET_FMT_lx " " TARGET_FMT_lx "\n",
> - __func__, ifetch ? 'I' : 'D', i, virtual,
> - *BATu, *BATl, BEPIu, BEPIl, bl);
> + qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx
> + " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx
> + "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " "
> + TARGET_FMT_lx "\n", __func__, ifetch ? 'I' : 'D',
> + i, virtual, *BATu, *BATl, BEPIu, BEPIl, bl);
> }
> }
> }
> @@ -400,9 +399,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> hash = vsid ^ pgidx;
> ctx->ptem = (vsid << 7) | (pgidx >> 10);
>
> - qemu_log_mask(CPU_LOG_MMU,
> - "pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
> - ctx->key, ds, ctx->nx, vsid);
> + qemu_log_mask(CPU_LOG_MMU, "pte segment: key=%d ds %d nx %d vsid "
> + TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid);
> ret = -1;
> if (!ds) {
> /* Check if instruction fetch is allowed, if needed */
> @@ -599,9 +597,9 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> return 0;
> }
> }
> - qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
> - " => " HWADDR_FMT_plx
> - " %d %d\n", __func__, address, raddr, ctx->prot, ret);
> + qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
> + " => " HWADDR_FMT_plx " %d %d\n",
> + __func__, address, raddr, ctx->prot, ret);
>
> return ret;
> }
> @@ -713,11 +711,11 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
> }
>
> mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
> - qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
> - " PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
> - HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
> - __func__, address, pid, tlb->mas1, tlb->mas2, mask,
> - tlb->mas7_3, tlb->mas8);
> + qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
> + " PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
> + HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
> + __func__, address, pid, tlb->mas1, tlb->mas2, mask,
> + tlb->mas7_3, tlb->mas8);
>
> /* Check PID */
> tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
2024-05-01 23:43 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-07 10:06 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:06 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Instead of putting a large block of code in an if, invert the
> condition and return early to be able to deindent the code block.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 319 ++++++++++++++++++++--------------------
> 1 file changed, 159 insertions(+), 160 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 28847c32f2..2487b4deff 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1265,187 +1265,186 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> *protp = ctx.prot;
> *psizep = TARGET_PAGE_BITS;
> return true;
> + } else if (!guest_visible) {
> + return false;
> }
Acked-by: Nicholas Piggin <npiggin@gmail.com>
>
> - if (guest_visible) {
> - log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> - if (type == ACCESS_CODE) {
> - switch (ret) {
> - case -1:
> - /* No matches in page tables or TLB */
> - switch (env->mmu_model) {
> - case POWERPC_MMU_SOFT_6xx:
> - cs->exception_index = POWERPC_EXCP_IFTLB;
> - env->error_code = 1 << 18;
> - env->spr[SPR_IMISS] = eaddr;
> - env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
> - goto tlb_miss;
> - case POWERPC_MMU_SOFT_4xx:
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->error_code = 0;
> - env->spr[SPR_40x_DEAR] = eaddr;
> - env->spr[SPR_40x_ESR] = 0x00000000;
> - break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
> - break;
> - case POWERPC_MMU_REAL:
> - cpu_abort(cs, "PowerPC in real mode should never raise "
> - "any MMU exceptions\n");
> - default:
> - cpu_abort(cs, "Unknown or invalid MMU model\n");
> - }
> + log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> + if (type == ACCESS_CODE) {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_SOFT_6xx:
> + cs->exception_index = POWERPC_EXCP_IFTLB;
> + env->error_code = 1 << 18;
> + env->spr[SPR_IMISS] = eaddr;
> + env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
> + goto tlb_miss;
> + case POWERPC_MMU_SOFT_4xx:
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->error_code = 0;
> + env->spr[SPR_40x_DEAR] = eaddr;
> + env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> - case -2:
> - /* Access rights violation */
> - cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x08000000;
> - }
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
> break;
> - case -3:
> - /* No execute protection violation */
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_ESR] = 0x00000000;
> - env->error_code = 0;
> + case POWERPC_MMU_REAL:
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> + "any MMU exceptions\n");
> + default:
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> + (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> + env->error_code = 0;
> + } else {
> + env->error_code = 0x08000000;
> + }
> + break;
> + case -3:
> + /* No execute protection violation */
> + if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> + (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> + env->spr[SPR_BOOKE_ESR] = 0x00000000;
> + env->error_code = 0;
> + } else {
> + env->error_code = 0x10000000;
> + }
> + cs->exception_index = POWERPC_EXCP_ISI;
> + break;
> + case -4:
> + /* Direct store exception */
> + /* No code fetch is allowed in direct-store areas */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> + (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> + env->error_code = 0;
> + } else {
> + env->error_code = 0x10000000;
> + }
> + break;
> + }
> + } else {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_SOFT_6xx:
> + if (access_type == MMU_DATA_STORE) {
> + cs->exception_index = POWERPC_EXCP_DSTLB;
> + env->error_code = 1 << 16;
> } else {
> - env->error_code = 0x10000000;
> + cs->exception_index = POWERPC_EXCP_DLTLB;
> + env->error_code = 0;
> }
> - cs->exception_index = POWERPC_EXCP_ISI;
> + env->spr[SPR_DMISS] = eaddr;
> + env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
> + tlb_miss:
> + env->error_code |= ctx.key << 19;
> + env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
> + get_pteg_offset32(cpu, ctx.hash[0]);
> + env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
> + get_pteg_offset32(cpu, ctx.hash[1]);
> break;
> - case -4:
> - /* Direct store exception */
> - /* No code fetch is allowed in direct-store areas */
> - cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> + case POWERPC_MMU_SOFT_4xx:
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->error_code = 0;
> + env->spr[SPR_40x_DEAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_40x_ESR] = 0x00800000;
> } else {
> - env->error_code = 0x10000000;
> + env->spr[SPR_40x_ESR] = 0x00000000;
> }
> break;
> - }
> - } else {
> - switch (ret) {
> - case -1:
> - /* No matches in page tables or TLB */
> - switch (env->mmu_model) {
> - case POWERPC_MMU_SOFT_6xx:
> - if (access_type == MMU_DATA_STORE) {
> - cs->exception_index = POWERPC_EXCP_DSTLB;
> - env->error_code = 1 << 16;
> - } else {
> - cs->exception_index = POWERPC_EXCP_DLTLB;
> - env->error_code = 0;
> - }
> - env->spr[SPR_DMISS] = eaddr;
> - env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
> - tlb_miss:
> - env->error_code |= ctx.key << 19;
> - env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
> - get_pteg_offset32(cpu, ctx.hash[0]);
> - env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
> - get_pteg_offset32(cpu, ctx.hash[1]);
> - break;
> - case POWERPC_MMU_SOFT_4xx:
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->error_code = 0;
> - env->spr[SPR_40x_DEAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_40x_ESR] = 0x00800000;
> - } else {
> - env->spr[SPR_40x_ESR] = 0x00000000;
> - }
> - break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> - case POWERPC_MMU_REAL:
> - cpu_abort(cs, "PowerPC in real mode should never raise "
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case POWERPC_MMU_REAL:
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> - default:
> - cpu_abort(cs, "Unknown or invalid MMU model\n");
> + default:
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
> + env->spr[SPR_40x_DEAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_40x_ESR] |= 0x00800000;
> }
> + } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> + (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + } else {
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x0A000000;
> + } else {
> + env->spr[SPR_DSISR] = 0x08000000;
> + }
> + }
> + break;
> + case -4:
> + /* Direct store exception */
> + switch (type) {
> + case ACCESS_FLOAT:
> + /* Floating point load/store */
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> + env->error_code = POWERPC_EXCP_ALIGN_FP;
> + env->spr[SPR_DAR] = eaddr;
> break;
> - case -2:
> - /* Access rights violation */
> + case ACCESS_RES:
> + /* lwarx, ldarx or stwcx. */
> cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> - if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
> - env->spr[SPR_40x_DEAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_40x_ESR] |= 0x00800000;
> - }
> - } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06000000;
> } else {
> - env->spr[SPR_DAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x0A000000;
> - } else {
> - env->spr[SPR_DSISR] = 0x08000000;
> - }
> + env->spr[SPR_DSISR] = 0x04000000;
> }
> break;
> - case -4:
> - /* Direct store exception */
> - switch (type) {
> - case ACCESS_FLOAT:
> - /* Floating point load/store */
> - cs->exception_index = POWERPC_EXCP_ALIGN;
> - env->error_code = POWERPC_EXCP_ALIGN_FP;
> - env->spr[SPR_DAR] = eaddr;
> - break;
> - case ACCESS_RES:
> - /* lwarx, ldarx or stwcx. */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - env->error_code = 0;
> - env->spr[SPR_DAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06000000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04000000;
> - }
> - break;
> - case ACCESS_EXT:
> - /* eciwx or ecowx */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - env->error_code = 0;
> - env->spr[SPR_DAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06100000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04100000;
> - }
> - break;
> - default:
> - printf("DSI: invalid exception (%d)\n", ret);
> - cs->exception_index = POWERPC_EXCP_PROGRAM;
> - env->error_code =
> - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> - env->spr[SPR_DAR] = eaddr;
> - break;
> + case ACCESS_EXT:
> + /* eciwx or ecowx */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06100000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04100000;
> }
> break;
> + default:
> + printf("DSI: invalid exception (%d)\n", ret);
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> + env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> + env->spr[SPR_DAR] = eaddr;
> + break;
> }
> + break;
> }
> }
> return false;
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate()
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-07 10:11 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:11 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The "2" in booke206_update_mas_tlb_miss() call corresponds to
> MMU_INST_FETCH which is the value of access_type in this branch;
> mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
> code access so using MMU_DATA_LOAD here seems wrong so replace it with
> access_type here as well that yields the same result. This also makes
> these calls the same as the data access branch further down.
Looks right.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 2487b4deff..762b13805b 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1288,13 +1288,13 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> /* fall through */
> case POWERPC_MMU_BOOKE:
> cs->exception_index = POWERPC_EXCP_ITLB;
> env->error_code = 0;
> env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> break;
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
@ 2024-05-07 10:47 ` Nicholas Piggin
2024-05-07 15:31 ` BALATON Zoltan
0 siblings, 1 reply; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:47 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is not used from any other files so make it static and
> fix the maybe used uninitialised warnings this has uncovered.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/internal.h | 5 +----
> target/ppc/mmu_common.c | 5 ++++-
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 601c0b533f..7a99f08dc8 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -261,10 +261,7 @@ typedef struct mmu_ctx_t mmu_ctx_t;
> bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> hwaddr *raddrp, int *psizep, int *protp,
> int mmu_idx, bool guest_visible);
> -int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> - target_ulong eaddr,
> - MMUAccessType access_type, int type,
> - int mmu_idx);
> +
> /* Software driven TLB helpers */
> int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
> int way, int is_code);
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 762b13805b..4852cb5571 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -666,6 +666,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> hwaddr raddr = (hwaddr)-1ULL;
> int i, ret = -1;
>
> + ctx->prot = 0;
> for (i = 0; i < env->nb_tlb; i++) {
> tlb = &env->tlb.tlbe[i];
> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> @@ -873,6 +874,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> hwaddr raddr = (hwaddr)-1ULL;
> int i, j, ways, ret = -1;
>
> + ctx->prot = 0;
> for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> ways = booke206_tlb_ways(env, i);
> for (j = 0; j < ways; j++) {
The prot warnings are valid AFAIKS, used uninit by qemu_log_mask call.
So, I see what the booke _check_tlb() functions are doing with
*prot now and that is to assign it iff return value is 0 or -2 or
-3, matching TLB address (and possibly mismatch prot).
Would it be better to fix it as:
qemu_log_mask(CPU_LOG_MMU,
"%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
" %d %d\n", __func__, ret < 0 ? "refused" : "granted",
address, raddr, ret == -1 ? 0 : ctx->prot, ret);
This way it's clearer that we're only printing it when a TLB was
found, and it won't silence other possible use-uninitialised?
> @@ -1144,7 +1146,7 @@ void dump_mmu(CPUPPCState *env)
> }
> }
>
> -int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> +static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> target_ulong eaddr,
> MMUAccessType access_type, int type,
> int mmu_idx)
> @@ -1163,6 +1165,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> env->mmu_model == POWERPC_MMU_REAL)) {
> + memset(ctx, 0, sizeof(*ctx));
> ctx->raddr = eaddr;
> ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> return 0;
I wonder why the compiler doesn't see these, they are all in the return
not-zero cases that should be quite visible?
What if you leave the static change to the end of your series, do the
simplifications allow the compiler to work it out? I prefer not to
squash such compiler warnings if it can be avoided.
Thanks,
Nick
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
@ 2024-05-07 10:49 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 10:49 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This type is only used within mmu_common.c. Move its definition from
> internal.h to there.
This can be squashed with the previous patch unexport the
remaining user.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/internal.h | 12 ------------
> target/ppc/mmu_common.c | 11 +++++++++++
> 2 files changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 7a99f08dc8..61c2aadd0d 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -256,8 +256,6 @@ static inline int prot_for_access_type(MMUAccessType access_type)
>
> /* PowerPC MMU emulation */
>
> -typedef struct mmu_ctx_t mmu_ctx_t;
> -
> bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> hwaddr *raddrp, int *psizep, int *protp,
> int mmu_idx, bool guest_visible);
> @@ -265,16 +263,6 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> /* Software driven TLB helpers */
> int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
> int way, int is_code);
> -/* Context used internally during MMU translations */
> -struct mmu_ctx_t {
> - hwaddr raddr; /* Real address */
> - hwaddr eaddr; /* Effective address */
> - int prot; /* Protection bits */
> - hwaddr hash[2]; /* Pagetable hash values */
> - target_ulong ptem; /* Virtual segment ID | API */
> - int key; /* Access key */
> - int nx; /* Non-execute area */
> -};
>
> #endif /* !CONFIG_USER_ONLY */
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 4852cb5571..41ef174ab4 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -35,6 +35,17 @@
>
> /* #define DUMP_PAGE_TABLES */
>
> +/* Context used internally during MMU translations */
> +typedef struct {
> + hwaddr raddr; /* Real address */
> + hwaddr eaddr; /* Effective address */
> + int prot; /* Protection bits */
> + hwaddr hash[2]; /* Pagetable hash values */
> + target_ulong ptem; /* Virtual segment ID | API */
> + int key; /* Access key */
> + int nx; /* Non-execute area */
> +} mmu_ctx_t;
> +
> void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> {
> PowerPCCPU *cpu = env_archcpu(env);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
@ 2024-05-07 11:35 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 11:35 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
> pp_check() in mmu_common.c. Rename the latter to ppc_pte_prot() and
> merge with ppc_hash32_pp_prot() to remove duplicated code.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/internal.h | 2 +-
> target/ppc/mmu-hash32.c | 47 +----------------------------------------
> target/ppc/mmu_common.c | 19 +++++++++--------
> 3 files changed, 12 insertions(+), 56 deletions(-)
>
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 61c2aadd0d..d7c923b017 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -255,7 +255,7 @@ static inline int prot_for_access_type(MMUAccessType access_type)
> #ifndef CONFIG_USER_ONLY
>
> /* PowerPC MMU emulation */
> -
> +int ppc_pte_prot(int key, int pp, int nx);
Hmm, these were split by 496272a7018. 64 was being split
out too at the time, so maybe not immediately obvious
they were the same.
Good consolidation but can you keep pp in the name?
It's taking ppc's PTE[pp] (page protection) field and
converting it to QEMU prot value.
ppc_hash32_pp_prot is probably fine, 6xx is hash too.
and could stay in mmu-hash32.c, so just use that
version unchanged?
Thanks,
Nick
> bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> hwaddr *raddrp, int *psizep, int *protp,
> int mmu_idx, bool guest_visible);
> diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
> index 3976416840..ee9df351ae 100644
> --- a/target/ppc/mmu-hash32.c
> +++ b/target/ppc/mmu-hash32.c
> @@ -42,51 +42,6 @@ struct mmu_ctx_hash32 {
> int key; /* Access key */
> };
>
> -static int ppc_hash32_pp_prot(int key, int pp, int nx)
> -{
> - int prot;
> -
> - if (key == 0) {
> - switch (pp) {
> - case 0x0:
> - case 0x1:
> - case 0x2:
> - prot = PAGE_READ | PAGE_WRITE;
> - break;
> -
> - case 0x3:
> - prot = PAGE_READ;
> - break;
> -
> - default:
> - abort();
> - }
> - } else {
> - switch (pp) {
> - case 0x0:
> - prot = 0;
> - break;
> -
> - case 0x1:
> - case 0x3:
> - prot = PAGE_READ;
> - break;
> -
> - case 0x2:
> - prot = PAGE_READ | PAGE_WRITE;
> - break;
> -
> - default:
> - abort();
> - }
> - }
> - if (nx == 0) {
> - prot |= PAGE_EXEC;
> - }
> -
> - return prot;
> -}
> -
> static int ppc_hash32_pte_prot(int mmu_idx,
> target_ulong sr, ppc_hash_pte32_t pte)
> {
> @@ -95,7 +50,7 @@ static int ppc_hash32_pte_prot(int mmu_idx,
> key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS));
> pp = pte.pte1 & HPTE32_R_PP;
>
> - return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
> + return ppc_pte_prot(key, pp, !!(sr & SR32_NX));
> }
>
> static target_ulong hash32_bat_size(int mmu_idx,
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 41ef174ab4..0ce5c1e841 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -75,22 +75,23 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> /*****************************************************************************/
> /* PowerPC MMU emulation */
>
> -static int pp_check(int key, int pp, int nx)
> +int ppc_pte_prot(int key, int pp, int nx)
> {
> int access;
>
> /* Compute access rights */
> - access = 0;
> if (key == 0) {
> switch (pp) {
> case 0x0:
> case 0x1:
> case 0x2:
> - access |= PAGE_WRITE;
> - /* fall through */
> + access = PAGE_READ | PAGE_WRITE;
> + break;
> case 0x3:
> - access |= PAGE_READ;
> + access = PAGE_READ;
> break;
> + default:
> + g_assert_not_reached();
> }
> } else {
> switch (pp) {
> @@ -104,6 +105,8 @@ static int pp_check(int key, int pp, int nx)
> case 0x2:
> access = PAGE_READ | PAGE_WRITE;
> break;
> + default:
> + g_assert_not_reached();
> }
> }
> if (nx == 0) {
> @@ -140,7 +143,7 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
> MMUAccessType access_type)
> {
> target_ulong ptem, mmask;
> - int access, ret, pteh, ptev, pp;
> + int ret, pteh, ptev, pp;
>
> ret = -1;
> /* Check validity and table match */
> @@ -159,11 +162,9 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
> return -3;
> }
> }
> - /* Compute access rights */
> - access = pp_check(ctx->key, pp, ctx->nx);
> /* Keep the matching PTE information */
> ctx->raddr = pte1;
> - ctx->prot = access;
> + ctx->prot = ppc_pte_prot(ctx->key, pp, ctx->nx);
> ret = check_prot(ctx->prot, access_type);
> if (ret == 0) {
> /* Access granted */
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
@ 2024-05-07 11:51 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 11:51 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
Nice.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 180 ++++++++++++++++++++++++++++++----------
> 1 file changed, 138 insertions(+), 42 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 0ce5c1e841..a1f98f8de4 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1250,6 +1250,137 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
> }
>
> +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> + MMUAccessType access_type,
> + hwaddr *raddrp, int *psizep, int *protp,
> + int mmu_idx, bool guest_visible)
> +{
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> + mmu_ctx_t ctx;
> + int ret;
> +
> + if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> + ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
> + mmu_idx);
> + } else {
> + ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
> + }
> + if (ret == 0) {
> + *raddrp = ctx.raddr;
> + *protp = ctx.prot;
> + *psizep = TARGET_PAGE_BITS;
> + return true;
> + } else if (!guest_visible) {
> + return false;
> + }
> +
> + log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> + if (access_type == MMU_INST_FETCH) {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0;
> + break;
> + case -3:
> + /* No execute protection violation */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->spr[SPR_BOOKE_ESR] = 0;
> + env->error_code = 0;
> + break;
> + case -4:
> + /* Direct store exception */
> + /* No code fetch is allowed in direct-store areas */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0;
> + break;
I don't think BookE has -4 (direct address translation) areas, it's
only 6xx by the looks.
You could put another patch before this to remove the BOOKE tests
from the ret == -4 cases, then avoid copying them in here.
Otherwise I think it looks okay.
Thanks,
Nick
> + }
> + } else {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -4:
> + /* Direct store exception */
> + switch (env->access_type) {
> + case ACCESS_FLOAT:
> + /* Floating point load/store */
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> + env->error_code = POWERPC_EXCP_ALIGN_FP;
> + env->spr[SPR_DAR] = eaddr;
> + break;
> + case ACCESS_RES:
> + /* lwarx, ldarx or stwcx. */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06000000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04000000;
> + }
> + break;
> + case ACCESS_EXT:
> + /* eciwx or ecowx */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06100000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04100000;
> + }
> + break;
> + default:
> + printf("DSI: invalid exception (%d)\n", ret);
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> + env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> + env->spr[SPR_DAR] = eaddr;
> + break;
> + }
> + break;
> + }
> + }
> + return false;
> +}
> +
> /* Perform address translation */
> /* TODO: Split this by mmu_model. */
> static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> @@ -1302,15 +1433,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_DEAR] = eaddr;
> env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> @@ -1321,34 +1443,18 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> case -2:
> /* Access rights violation */
> cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x08000000;
> - }
> + env->error_code = 0x08000000;
> break;
> case -3:
> /* No execute protection violation */
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_ESR] = 0x00000000;
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x10000000;
> - }
> cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0x10000000;
> break;
> case -4:
> /* Direct store exception */
> /* No code fetch is allowed in direct-store areas */
> cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x10000000;
> - }
> + env->error_code = 0x10000000;
> break;
> }
> } else {
> @@ -1383,15 +1489,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_ESR] = 0x00000000;
> }
> break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> @@ -1408,10 +1505,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> if (access_type == MMU_DATA_STORE) {
> env->spr[SPR_40x_ESR] |= 0x00800000;
> }
> - } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> } else {
> env->spr[SPR_DAR] = eaddr;
> if (access_type == MMU_DATA_STORE) {
> @@ -1490,7 +1583,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> case POWERPC_MMU_32B:
> return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
> psizep, protp, mmu_idx, guest_visible);
> -
> + case POWERPC_MMU_BOOKE:
> + case POWERPC_MMU_BOOKE206:
> + return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
> + psizep, protp, mmu_idx, guest_visible);
> default:
> return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp,
> psizep, protp, mmu_idx, guest_visible);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
@ 2024-05-07 12:05 ` Nicholas Piggin
2024-05-07 23:40 ` BALATON Zoltan
0 siblings, 1 reply; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:05 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is no longer called for BookE MMU model so remove parts
> related to it. This has uncovered a few may be used uninitialised
> warnings that are also fixed.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 25 +++++--------------------
> 1 file changed, 5 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index a1f98f8de4..d61c41d8c9 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -684,12 +684,10 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> access_type, i);
> if (ret != -1) {
> - if (ret >= 0) {
> - ctx->raddr = raddr;
> - }
> break;
> }
> }
> + ctx->raddr = raddr;
> qemu_log_mask(CPU_LOG_MMU,
> "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
> " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
> @@ -897,9 +895,6 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> access_type, mmu_idx);
> if (ret != -1) {
> - if (ret >= 0) {
> - ctx->raddr = raddr;
> - }
> goto found_tlb;
> }
> }
> @@ -907,6 +902,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>
> found_tlb:
>
> + ctx->raddr = raddr;
Not sure about the uninitialized warnings here either, caller probably
should not be using ctx->raddr unless we returned 0...
> qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
> HWADDR_FMT_plx " %d %d\n", __func__,
> ret < 0 ? "refused" : "granted", address, raddr,
> @@ -1163,20 +1159,9 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> MMUAccessType access_type, int type,
> int mmu_idx)
> {
> - bool real_mode;
> -
> - if (env->mmu_model == POWERPC_MMU_BOOKE) {
> - return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
> - } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> - return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
> - mmu_idx);
> - }
This could just go in the previous patch when you split booke xlate?
> -
> - real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> - : !FIELD_EX64(env->msr, MSR, DR);
> - if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> - env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> - env->mmu_model == POWERPC_MMU_REAL)) {
> + bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> + : !FIELD_EX64(env->msr, MSR, DR);
> + if (real_mode) {
> memset(ctx, 0, sizeof(*ctx));
> ctx->raddr = eaddr;
> ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
This still changes beahviour of MPC8xx MMU doesn't it? It's supposed
to abort always.
Thanks,
Nick
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate()
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
@ 2024-05-07 12:15 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:15 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
Will review this if we can get -4 case removed...
Don't know if I'm too keen on doing the fetch branch first
and asymmetric (if vs switch) checking of ret in the fetch
vs data cases. I think with -4 case removed things will
look much nicer.
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 147 +++++++++++++++-------------------------
> 1 file changed, 56 insertions(+), 91 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index d61c41d8c9..b76611da80 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1261,106 +1261,71 @@ static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> }
>
> log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> + env->error_code = 0;
> + if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + }
> if (access_type == MMU_INST_FETCH) {
> - switch (ret) {
> - case -1:
> + if (ret == -1) {
> /* No matches in page tables or TLB */
> - switch (env->mmu_model) {
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - break;
> - case -2:
> - /* Access rights violation */
> - cs->exception_index = POWERPC_EXCP_ISI;
> - env->error_code = 0;
> - break;
> - case -3:
> - /* No execute protection violation */
> - cs->exception_index = POWERPC_EXCP_ISI;
> - env->spr[SPR_BOOKE_ESR] = 0;
> - env->error_code = 0;
> - break;
> - case -4:
> - /* Direct store exception */
> - /* No code fetch is allowed in direct-store areas */
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + } else {
> cs->exception_index = POWERPC_EXCP_ISI;
> - env->error_code = 0;
> - break;
> - }
> - } else {
> - switch (ret) {
> - case -1:
> - /* No matches in page tables or TLB */
> - switch (env->mmu_model) {
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> - default:
> - g_assert_not_reached();
> + if (ret == -3) {
> + /* No execute protection violation */
> + env->spr[SPR_BOOKE_ESR] = 0;
> }
> + }
> + return false;
> + }
> +
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -4:
> + /* Direct store exception */
> + env->spr[SPR_DAR] = eaddr;
> + switch (env->access_type) {
> + case ACCESS_FLOAT:
> + /* Floating point load/store */
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> + env->error_code = POWERPC_EXCP_ALIGN_FP;
> break;
> - case -2:
> - /* Access rights violation */
> + case ACCESS_RES:
> + /* lwarx, ldarx or stwcx. */
> cs->exception_index = POWERPC_EXCP_DSI;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06000000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04000000;
> + }
> break;
> - case -4:
> - /* Direct store exception */
> - switch (env->access_type) {
> - case ACCESS_FLOAT:
> - /* Floating point load/store */
> - cs->exception_index = POWERPC_EXCP_ALIGN;
> - env->error_code = POWERPC_EXCP_ALIGN_FP;
> - env->spr[SPR_DAR] = eaddr;
> - break;
> - case ACCESS_RES:
> - /* lwarx, ldarx or stwcx. */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - env->error_code = 0;
> - env->spr[SPR_DAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06000000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04000000;
> - }
> - break;
> - case ACCESS_EXT:
> - /* eciwx or ecowx */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - env->error_code = 0;
> - env->spr[SPR_DAR] = eaddr;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06100000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04100000;
> - }
> - break;
> - default:
> - printf("DSI: invalid exception (%d)\n", ret);
> - cs->exception_index = POWERPC_EXCP_PROGRAM;
> - env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> - env->spr[SPR_DAR] = eaddr;
> - break;
> + case ACCESS_EXT:
> + /* eciwx or ecowx */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06100000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04100000;
> }
> break;
> + default:
> + printf("DSI: invalid exception (%d)\n", ret);
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> + env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> + break;
> }
> }
> return false;
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
@ 2024-05-07 12:17 ` Nicholas Piggin
2024-05-07 12:31 ` BALATON Zoltan
2024-05-07 15:54 ` BALATON Zoltan
0 siblings, 2 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:17 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
What do you think about adding mmu-book3e.c instead?
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 300 ++++++++++++++++++++--------------------
> 1 file changed, 150 insertions(+), 150 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index b76611da80..204b8af455 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -910,6 +910,156 @@ found_tlb:
> return ret;
> }
>
> +static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> + MMUAccessType access_type, int mmu_idx)
> +{
> + uint32_t epid;
> + bool as, pr;
> + uint32_t missed_tid = 0;
> + bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
> +
> + if (access_type == MMU_INST_FETCH) {
> + as = FIELD_EX64(env->msr, MSR, IR);
> + }
> + env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
> + env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
> + env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
> + env->spr[SPR_BOOKE_MAS3] = 0;
> + env->spr[SPR_BOOKE_MAS6] = 0;
> + env->spr[SPR_BOOKE_MAS7] = 0;
> +
> + /* AS */
> + if (as) {
> + env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
> + env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
> + }
> +
> + env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
> + env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
> +
> + if (!use_epid) {
> + switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
> + case MAS4_TIDSELD_PID0:
> + missed_tid = env->spr[SPR_BOOKE_PID];
> + break;
> + case MAS4_TIDSELD_PID1:
> + missed_tid = env->spr[SPR_BOOKE_PID1];
> + break;
> + case MAS4_TIDSELD_PID2:
> + missed_tid = env->spr[SPR_BOOKE_PID2];
> + break;
> + }
> + env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
> + } else {
> + missed_tid = epid;
> + env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
> + }
> + env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
> +
> +
> + /* next victim logic */
> + env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
> + env->last_way++;
> + env->last_way &= booke206_tlb_ways(env, 0) - 1;
> + env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
> +}
> +
> +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> + MMUAccessType access_type,
> + hwaddr *raddrp, int *psizep, int *protp,
> + int mmu_idx, bool guest_visible)
> +{
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> + mmu_ctx_t ctx;
> + int ret;
> +
> + if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> + ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
> + mmu_idx);
> + } else {
> + ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
> + }
> + if (ret == 0) {
> + *raddrp = ctx.raddr;
> + *protp = ctx.prot;
> + *psizep = TARGET_PAGE_BITS;
> + return true;
> + } else if (!guest_visible) {
> + return false;
> + }
> +
> + log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> + env->error_code = 0;
> + if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + }
> + if (access_type == MMU_INST_FETCH) {
> + if (ret == -1) {
> + /* No matches in page tables or TLB */
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + } else {
> + cs->exception_index = POWERPC_EXCP_ISI;
> + if (ret == -3) {
> + /* No execute protection violation */
> + env->spr[SPR_BOOKE_ESR] = 0;
> + }
> + }
> + return false;
> + }
> +
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -4:
> + /* Direct store exception */
> + env->spr[SPR_DAR] = eaddr;
> + switch (env->access_type) {
> + case ACCESS_FLOAT:
> + /* Floating point load/store */
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> + env->error_code = POWERPC_EXCP_ALIGN_FP;
> + break;
> + case ACCESS_RES:
> + /* lwarx, ldarx or stwcx. */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06000000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04000000;
> + }
> + break;
> + case ACCESS_EXT:
> + /* eciwx or ecowx */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06100000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04100000;
> + }
> + break;
> + default:
> + printf("DSI: invalid exception (%d)\n", ret);
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> + env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> + break;
> + }
> + }
> + return false;
> +}
> +
> static const char *book3e_tsize_to_str[32] = {
> "1K", "2K", "4K", "8K", "16K", "32K", "64K", "128K", "256K", "512K",
> "1M", "2M", "4M", "8M", "16M", "32M", "64M", "128M", "256M", "512M",
> @@ -1181,156 +1331,6 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> }
> }
>
> -static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> - MMUAccessType access_type, int mmu_idx)
> -{
> - uint32_t epid;
> - bool as, pr;
> - uint32_t missed_tid = 0;
> - bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
> -
> - if (access_type == MMU_INST_FETCH) {
> - as = FIELD_EX64(env->msr, MSR, IR);
> - }
> - env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
> - env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
> - env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
> - env->spr[SPR_BOOKE_MAS3] = 0;
> - env->spr[SPR_BOOKE_MAS6] = 0;
> - env->spr[SPR_BOOKE_MAS7] = 0;
> -
> - /* AS */
> - if (as) {
> - env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
> - env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
> - }
> -
> - env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
> - env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
> -
> - if (!use_epid) {
> - switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
> - case MAS4_TIDSELD_PID0:
> - missed_tid = env->spr[SPR_BOOKE_PID];
> - break;
> - case MAS4_TIDSELD_PID1:
> - missed_tid = env->spr[SPR_BOOKE_PID1];
> - break;
> - case MAS4_TIDSELD_PID2:
> - missed_tid = env->spr[SPR_BOOKE_PID2];
> - break;
> - }
> - env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
> - } else {
> - missed_tid = epid;
> - env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
> - }
> - env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
> -
> -
> - /* next victim logic */
> - env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
> - env->last_way++;
> - env->last_way &= booke206_tlb_ways(env, 0) - 1;
> - env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
> -}
> -
> -static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> - MMUAccessType access_type,
> - hwaddr *raddrp, int *psizep, int *protp,
> - int mmu_idx, bool guest_visible)
> -{
> - CPUState *cs = CPU(cpu);
> - CPUPPCState *env = &cpu->env;
> - mmu_ctx_t ctx;
> - int ret;
> -
> - if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> - ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
> - mmu_idx);
> - } else {
> - ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
> - }
> - if (ret == 0) {
> - *raddrp = ctx.raddr;
> - *protp = ctx.prot;
> - *psizep = TARGET_PAGE_BITS;
> - return true;
> - } else if (!guest_visible) {
> - return false;
> - }
> -
> - log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> - env->error_code = 0;
> - if (env->mmu_model == POWERPC_MMU_BOOKE206 && ret == -1) {
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - }
> - if (access_type == MMU_INST_FETCH) {
> - if (ret == -1) {
> - /* No matches in page tables or TLB */
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - } else {
> - cs->exception_index = POWERPC_EXCP_ISI;
> - if (ret == -3) {
> - /* No execute protection violation */
> - env->spr[SPR_BOOKE_ESR] = 0;
> - }
> - }
> - return false;
> - }
> -
> - switch (ret) {
> - case -1:
> - /* No matches in page tables or TLB */
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> - case -2:
> - /* Access rights violation */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> - case -4:
> - /* Direct store exception */
> - env->spr[SPR_DAR] = eaddr;
> - switch (env->access_type) {
> - case ACCESS_FLOAT:
> - /* Floating point load/store */
> - cs->exception_index = POWERPC_EXCP_ALIGN;
> - env->error_code = POWERPC_EXCP_ALIGN_FP;
> - break;
> - case ACCESS_RES:
> - /* lwarx, ldarx or stwcx. */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06000000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04000000;
> - }
> - break;
> - case ACCESS_EXT:
> - /* eciwx or ecowx */
> - cs->exception_index = POWERPC_EXCP_DSI;
> - if (access_type == MMU_DATA_STORE) {
> - env->spr[SPR_DSISR] = 0x06100000;
> - } else {
> - env->spr[SPR_DSISR] = 0x04100000;
> - }
> - break;
> - default:
> - printf("DSI: invalid exception (%d)\n", ret);
> - cs->exception_index = POWERPC_EXCP_PROGRAM;
> - env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> - break;
> - }
> - }
> - return false;
> -}
> -
> /* Perform address translation */
> /* TODO: Split this by mmu_model. */
> static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
@ 2024-05-07 12:30 ` Nicholas Piggin
2024-05-07 16:02 ` BALATON Zoltan
0 siblings, 1 reply; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:30 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This flag for split instruction/data TLBs is only set for 6xx soft TLB
> MMU model and not used otherwise so no need to have a separate flag
> for that.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/pegasos2.c | 2 +-
> target/ppc/cpu.h | 1 -
> target/ppc/cpu_init.c | 19 +++++--------------
> target/ppc/helper_regs.c | 1 -
> target/ppc/mmu_common.c | 10 ++--------
> target/ppc/mmu_helper.c | 12 ++----------
> 6 files changed, 10 insertions(+), 35 deletions(-)
>
> diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
> index 04d6decb2b..dfc6fab180 100644
> --- a/hw/ppc/pegasos2.c
> +++ b/hw/ppc/pegasos2.c
> @@ -984,7 +984,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
> cpu->env.icache_line_size);
> qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
> cpu->env.icache_line_size);
> - if (cpu->env.id_tlbs) {
> + if (cpu->env.tlb_type == TLB_6XX) {
Want to just add the standard comment here?
/* 6xx has separate TLBs for instructions and data */
Otherwise looks good
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
> qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
> qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 0ac55d6b25..21e12a4f0d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1260,7 +1260,6 @@ struct CPUArchState {
> int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
> int nb_ways; /* Number of ways in the TLB set */
> int last_way; /* Last used way used to allocate TLB in a LRU way */
> - int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
> int nb_pids; /* Number of available PID registers */
> int tlb_type; /* Type of TLB we're dealing with */
> ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index c11a69fd90..07ad788e54 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2117,7 +2117,6 @@ static void init_proc_405(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> env->nb_ways = 1;
> - env->id_tlbs = 0;
> env->tlb_type = TLB_EMB;
> #endif
> init_excp_4xx(env);
> @@ -2190,7 +2189,6 @@ static void init_proc_440EP(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> env->nb_ways = 1;
> - env->id_tlbs = 0;
> env->tlb_type = TLB_EMB;
> #endif
> init_excp_BookE(env);
> @@ -2288,7 +2286,6 @@ static void init_proc_440GP(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> env->nb_ways = 1;
> - env->id_tlbs = 0;
> env->tlb_type = TLB_EMB;
> #endif
> init_excp_BookE(env);
> @@ -2362,7 +2359,6 @@ static void init_proc_440x5(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> env->nb_ways = 1;
> - env->id_tlbs = 0;
> env->tlb_type = TLB_EMB;
> #endif
> init_excp_BookE(env);
> @@ -2724,7 +2720,6 @@ static void init_proc_e200(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> env->nb_ways = 1;
> - env->id_tlbs = 0;
> env->tlb_type = TLB_EMB;
> #endif
> init_excp_e200(env, 0xFFFF0000UL);
> @@ -2843,7 +2838,6 @@ static void init_proc_e500(CPUPPCState *env, int version)
> /* Memory management */
> env->nb_pids = 3;
> env->nb_ways = 2;
> - env->id_tlbs = 0;
> switch (version) {
> case fsl_e500v1:
> tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
> @@ -6800,20 +6794,17 @@ static void init_ppc_proc(PowerPCCPU *cpu)
> }
> /* Allocate TLBs buffer when needed */
> #if !defined(CONFIG_USER_ONLY)
> - if (env->nb_tlb != 0) {
> - int nb_tlb = env->nb_tlb;
> - if (env->id_tlbs != 0) {
> - nb_tlb *= 2;
> - }
> + if (env->nb_tlb) {
> switch (env->tlb_type) {
> case TLB_6XX:
> - env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
> + /* 6xx has separate TLBs for instructions and data hence times 2 */
> + env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
> break;
> case TLB_EMB:
> - env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
> + env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
> break;
> case TLB_MAS:
> - env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
> + env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
> break;
> }
> /* Pre-compute some useful values */
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 25258986e3..ed583fe9b3 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -693,7 +693,6 @@ void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = nb_tlbs;
> env->nb_ways = nb_ways;
> - env->id_tlbs = 1;
> env->tlb_type = TLB_6XX;
> spr_register(env, SPR_DMISS, "DMISS",
> SPR_NOACCESS, SPR_NOACCESS,
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 204b8af455..a0b34f9637 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -130,8 +130,8 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
> nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
> /* Select TLB way */
> nr += env->tlb_per_way * way;
> - /* 6xx have separate TLBs for instructions and data */
> - if (is_code && env->id_tlbs == 1) {
> + /* 6xx has separate TLBs for instructions and data */
> + if (is_code) {
> nr += env->nb_tlb;
> }
>
> @@ -1246,13 +1246,7 @@ static void mmu6xx_dump_mmu(CPUPPCState *env)
> mmu6xx_dump_BATs(env, ACCESS_INT);
> mmu6xx_dump_BATs(env, ACCESS_CODE);
>
> - if (env->id_tlbs != 1) {
> - qemu_printf("ERROR: 6xx MMU should have separated TLB"
> - " for code and data\n");
> - }
> -
> qemu_printf("\nTLBs [EPN EPN + SIZE]\n");
> -
> for (type = 0; type < 2; type++) {
> for (way = 0; way < env->nb_ways; way++) {
> for (entry = env->nb_tlb * type + env->tlb_per_way * way;
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 817836b731..87c611888b 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -44,14 +44,8 @@
> static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
> {
> ppc6xx_tlb_t *tlb;
> - int nr, max;
> + int nr, max = 2 * env->nb_tlb;
>
> - /* LOG_SWTLB("Invalidate all TLBs\n"); */
> - /* Invalidate all defined software TLB */
> - max = env->nb_tlb;
> - if (env->id_tlbs == 1) {
> - max *= 2;
> - }
> for (nr = 0; nr < max; nr++) {
> tlb = &env->tlb.tlb6[nr];
> pte_invalidate(&tlb->pte0);
> @@ -307,9 +301,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> ppc6xx_tlb_invalidate_virt(env, addr, 0);
> - if (env->id_tlbs == 1) {
> - ppc6xx_tlb_invalidate_virt(env, addr, 1);
> - }
> + ppc6xx_tlb_invalidate_virt(env, addr, 1);
> break;
> case POWERPC_MMU_32B:
> /*
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-07 12:17 ` Nicholas Piggin
@ 2024-05-07 12:31 ` BALATON Zoltan
2024-05-08 12:30 ` Nicholas Piggin
2024-05-07 15:54 ` BALATON Zoltan
1 sibling, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 12:31 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> What do you think about adding mmu-book3e.c instead?
I have considered that but found that some functions have to be in the
same file and declared static for the compiler to inline them otherwise I
get worse performance. Maybe after these rearrangments it's now possible
to move these out but as this series got a bit long already I dod not go
through with that and left it for a follow up but I can give it a try.
Thanks for the review so far, I'll try to make the changes that I
understood and submit and updated version. I'm not sure I got some of your
requests so that may need another round.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
@ 2024-05-07 12:40 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:40 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Several 4xx related CPUs have the same TLB settings. Split it off in a
> common function in cpu_init.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/cpu_init.c | 46 ++++++++++++++++---------------------------
> 1 file changed, 17 insertions(+), 29 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 07ad788e54..d7e85c1b07 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2107,18 +2107,22 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
> return 0;
> }
>
> +static void init_tlbs_4xx(CPUPPCState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> + env->nb_tlb = 64;
> + env->nb_ways = 1;
> + env->tlb_type = TLB_EMB;
> +#endif
> +}
e200 isn't 4xx though is it? Call it init_TLB_EMB()?
Otherwise,
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Thanks,
Nick
> +
> static void init_proc_405(CPUPPCState *env)
> {
> register_40x_sprs(env);
> register_405_sprs(env);
> register_usprgh_sprs(env);
>
> - /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->tlb_type = TLB_EMB;
> -#endif
> + init_tlbs_4xx(env);
> init_excp_4xx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2185,12 +2189,8 @@ static void init_proc_440EP(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> - /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->tlb_type = TLB_EMB;
> -#endif
> +
> + init_tlbs_4xx(env);
> init_excp_BookE(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2282,12 +2282,7 @@ static void init_proc_440GP(CPUPPCState *env)
> register_440_sprs(env);
> register_usprgh_sprs(env);
>
> - /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->tlb_type = TLB_EMB;
> -#endif
> + init_tlbs_4xx(env);
> init_excp_BookE(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2355,12 +2350,8 @@ static void init_proc_440x5(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> - /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->tlb_type = TLB_EMB;
> -#endif
> +
> + init_tlbs_4xx(env);
> init_excp_BookE(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2717,11 +2708,8 @@ static void init_proc_e200(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->tlb_type = TLB_EMB;
> -#endif
> +
> + init_tlbs_4xx(env);
> init_excp_e200(env, 0xFFFF0000UL);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
` (27 preceding siblings ...)
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
@ 2024-05-07 12:45 ` Nicholas Piggin
2024-05-07 12:51 ` BALATON Zoltan
28 siblings, 1 reply; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-07 12:45 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The first 3 patches are
> from the last exception handling clean up series that were dropped due
> to some error on CI but I'm not sure if that was because of some CI
> infrastructure problem or some problem with the patches as the error
> did not make much sense. So these patches are only rebased now, I made
> no other change to them until the issue is understood better. The rest
> are new patches I've added since tha last series. Please review.
Not CI infrastructure as far as I could tell it's upstream gitlab.
But I could not figure out how to reproduce at the time... I ended
up running out of time to look too closely though.
I think I won't take the first 2, yes arguably the CPU does execute
the sc instruction, but it's actually a good rule for the exception
handler to be invoked with the nip that caused the exception, and
SRR0/1 to be set by the handler according to semantics.
Thanks,
Nick
>
> v2:
> - Fix user mode issue in patch 1 by keeping old behaviour for user mode
> - Add some more MMU clean up patches
>
> Regards,
> BALATON Zoltan
>
> BALATON Zoltan (28):
> target/ppc: Fix gen_sc to use correct nip
> target/ppc: Move patching nip from exception handler to helper_scv
> target/ppc: Simplify syscall exception handlers
> target/ppc: Remove unused helper
> target/ppc/mmu_common.c: Move calculation of a value closer to its
> usage
> target/ppc/mmu_common.c: Move calculation of a value closer to its
> usage
> target/ppc/mmu_common.c: Remove unneeded local variable
> target/ppc/mmu_common.c: Simplify checking for real mode
> target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU
> target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()
> target/ppc/mmu_common.c: Rename get_bat_6xx_tlb()
> target/ppc/mmu_common.c: Split out BookE cases before checking real
> mode
> target/ppc/mmu_common.c: Split off real mode cases in
> get_physical_address_wtlb()
> target/ppc/mmu_common.c: Inline and remove check_physical()
> target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address()
> target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address()
> target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls
> target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
> target/ppc/mmu_common.c: Replace hard coded constants in
> ppc_jumbo_xlate()
> target/ppc/mmu_common.c: Make get_physical_address_wtlb() static
> target/ppc: Move mmu_ctx_t definition to mmu_common.c
> target/ppc: Remove ppc_hash32_pp_prot() and reuse common function
> target/ppc/mmu_common.c: Split off BookE handling from
> ppc_jumbo_xlate()
> target/ppc/mmu_common.c: Remove BookE handling from
> get_physical_address_wtlb()
> target/ppc/mmu_common.c: Simplify ppc_booke_xlate()
> target/ppc/mmu_common.c: Move BookE MMU functions together
> target/ppc: Remove id_tlbs flag from CPU env
> target/ppc: Split off common 4xx TLB init
>
> hw/ppc/pegasos2.c | 2 +-
> target/ppc/cpu.h | 1 -
> target/ppc/cpu_init.c | 65 ++--
> target/ppc/excp_helper.c | 67 +---
> target/ppc/helper.h | 2 -
> target/ppc/helper_regs.c | 1 -
> target/ppc/internal.h | 19 +-
> target/ppc/mmu-hash32.c | 47 +--
> target/ppc/mmu_common.c | 792 +++++++++++++++++++--------------------
> target/ppc/mmu_helper.c | 36 +-
> target/ppc/translate.c | 21 +-
> 11 files changed, 438 insertions(+), 615 deletions(-)
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
@ 2024-05-07 12:51 ` BALATON Zoltan
0 siblings, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 12:51 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
>> This series does some further clean up mostly around BookE MMU to
>> untangle it from other MMU models. It also contains some other changes
>> that I've come up with while working on this. The first 3 patches are
>> from the last exception handling clean up series that were dropped due
>> to some error on CI but I'm not sure if that was because of some CI
>> infrastructure problem or some problem with the patches as the error
>> did not make much sense. So these patches are only rebased now, I made
>> no other change to them until the issue is understood better. The rest
>> are new patches I've added since tha last series. Please review.
>
> Not CI infrastructure as far as I could tell it's upstream gitlab.
> But I could not figure out how to reproduce at the time... I ended
> up running out of time to look too closely though.
I could reproduce it at the end so it wasn't CI failure but I don't
completely understand what is it.
> I think I won't take the first 2, yes arguably the CPU does execute
> the sc instruction, but it's actually a good rule for the exception
> handler to be invoked with the nip that caused the exception, and
> SRR0/1 to be set by the handler according to semantics.
>>
>> v2:
>> - Fix user mode issue in patch 1 by keeping old behaviour for user mode
I forgot to change the blurb above but in this v2 version I think I've
solved that problem as noted here but I don't know why the user mode SC is
different and could not find where is it handled. This version seems to
work though.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static
2024-05-07 10:47 ` Nicholas Piggin
@ 2024-05-07 15:31 ` BALATON Zoltan
0 siblings, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 15:31 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
>> This function is not used from any other files so make it static and
>> fix the maybe used uninitialised warnings this has uncovered.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> target/ppc/internal.h | 5 +----
>> target/ppc/mmu_common.c | 5 ++++-
>> 2 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
>> index 601c0b533f..7a99f08dc8 100644
>> --- a/target/ppc/internal.h
>> +++ b/target/ppc/internal.h
>> @@ -261,10 +261,7 @@ typedef struct mmu_ctx_t mmu_ctx_t;
>> bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
>> hwaddr *raddrp, int *psizep, int *protp,
>> int mmu_idx, bool guest_visible);
>> -int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>> - target_ulong eaddr,
>> - MMUAccessType access_type, int type,
>> - int mmu_idx);
>> +
>> /* Software driven TLB helpers */
>> int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
>> int way, int is_code);
>> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
>> index 762b13805b..4852cb5571 100644
>> --- a/target/ppc/mmu_common.c
>> +++ b/target/ppc/mmu_common.c
>> @@ -666,6 +666,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>> hwaddr raddr = (hwaddr)-1ULL;
>> int i, ret = -1;
>>
>> + ctx->prot = 0;
>> for (i = 0; i < env->nb_tlb; i++) {
>> tlb = &env->tlb.tlbe[i];
>> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
>> @@ -873,6 +874,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>> hwaddr raddr = (hwaddr)-1ULL;
>> int i, j, ways, ret = -1;
>>
>> + ctx->prot = 0;
>> for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
>> ways = booke206_tlb_ways(env, i);
>> for (j = 0; j < ways; j++) {
>
> The prot warnings are valid AFAIKS, used uninit by qemu_log_mask call.
>
> So, I see what the booke _check_tlb() functions are doing with
> *prot now and that is to assign it iff return value is 0 or -2 or
> -3, matching TLB address (and possibly mismatch prot).
>
> Would it be better to fix it as:
>
> qemu_log_mask(CPU_LOG_MMU,
> "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
> " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
> address, raddr, ret == -1 ? 0 : ctx->prot, ret);
>
> This way it's clearer that we're only printing it when a TLB was
> found, and it won't silence other possible use-uninitialised?
I can do that.
>> @@ -1144,7 +1146,7 @@ void dump_mmu(CPUPPCState *env)
>> }
>> }
>>
>> -int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>> +static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>> target_ulong eaddr,
>> MMUAccessType access_type, int type,
>> int mmu_idx)
>> @@ -1163,6 +1165,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>> if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
>> env->mmu_model == POWERPC_MMU_SOFT_4xx ||
>> env->mmu_model == POWERPC_MMU_REAL)) {
>> + memset(ctx, 0, sizeof(*ctx));
>> ctx->raddr = eaddr;
>> ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>> return 0;
>
> I wonder why the compiler doesn't see these, they are all in the return
> not-zero cases that should be quite visible?
>
> What if you leave the static change to the end of your series, do the
> simplifications allow the compiler to work it out? I prefer not to
> squash such compiler warnings if it can be avoided.
Even removing this memser at the end of the series brings back the
warnings so this has to stay for now. Maybe this can be cleaned up later
but I'd like to focus on booke now.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-07 12:17 ` Nicholas Piggin
2024-05-07 12:31 ` BALATON Zoltan
@ 2024-05-07 15:54 ` BALATON Zoltan
1 sibling, 0 replies; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 15:54 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> What do you think about adding mmu-book3e.c instead?
Now I remember that besides possible performance loss because of loss of
automatic inline if not all functions are static the other reason was that
these functions use mmu_ctx_t that I don't want to export. Howerver these
booke functions only use the raddr and ctx fields so there should be no
reason to use the ctx and I had a patch to do that but dropped it trying
to simplify the series and come back to it later. I might try to get that
back to see if it helps with some used uninit warnings but I'm not sure it
would.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env
2024-05-07 12:30 ` Nicholas Piggin
@ 2024-05-07 16:02 ` BALATON Zoltan
2024-05-08 12:37 ` Nicholas Piggin
0 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 16:02 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
>> This flag for split instruction/data TLBs is only set for 6xx soft TLB
>> MMU model and not used otherwise so no need to have a separate flag
>> for that.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/pegasos2.c | 2 +-
>> target/ppc/cpu.h | 1 -
>> target/ppc/cpu_init.c | 19 +++++--------------
>> target/ppc/helper_regs.c | 1 -
>> target/ppc/mmu_common.c | 10 ++--------
>> target/ppc/mmu_helper.c | 12 ++----------
>> 6 files changed, 10 insertions(+), 35 deletions(-)
>>
>> diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
>> index 04d6decb2b..dfc6fab180 100644
>> --- a/hw/ppc/pegasos2.c
>> +++ b/hw/ppc/pegasos2.c
>> @@ -984,7 +984,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
>> cpu->env.icache_line_size);
>> qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
>> cpu->env.icache_line_size);
>> - if (cpu->env.id_tlbs) {
>> + if (cpu->env.tlb_type == TLB_6XX) {
>
> Want to just add the standard comment here?
>
> /* 6xx has separate TLBs for instructions and data */
I think that comment would be redundant here because it's clear from the
i-tlb, d-tlb this adds so I can do without a comment in this machine if
you don't mind. (If this was not in my machine I would not mind adding a
comment but I'd keep this one simple.) I think comments should only be
added for things that are not clear from code.
Regards,
BALATON Zoltan
> Otherwise looks good
>
> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
>> qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
>> qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
>> qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()
2024-05-07 12:05 ` Nicholas Piggin
@ 2024-05-07 23:40 ` BALATON Zoltan
2024-05-08 12:54 ` Nicholas Piggin
0 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-07 23:40 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue, 7 May 2024, Nicholas Piggin wrote:
> On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
>> This function is no longer called for BookE MMU model so remove parts
>> related to it. This has uncovered a few may be used uninitialised
>> warnings that are also fixed.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> target/ppc/mmu_common.c | 25 +++++--------------------
>> 1 file changed, 5 insertions(+), 20 deletions(-)
>>
>> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
>> index a1f98f8de4..d61c41d8c9 100644
>> --- a/target/ppc/mmu_common.c
>> +++ b/target/ppc/mmu_common.c
>> @@ -684,12 +684,10 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
>> access_type, i);
>> if (ret != -1) {
>> - if (ret >= 0) {
>> - ctx->raddr = raddr;
>> - }
>> break;
>> }
>> }
>> + ctx->raddr = raddr;
>> qemu_log_mask(CPU_LOG_MMU,
>> "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
>> " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
>> @@ -897,9 +895,6 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>> ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
>> access_type, mmu_idx);
>> if (ret != -1) {
>> - if (ret >= 0) {
>> - ctx->raddr = raddr;
>> - }
>> goto found_tlb;
>> }
>> }
>> @@ -907,6 +902,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>>
>> found_tlb:
>>
>> + ctx->raddr = raddr;
>
> Not sure about the uninitialized warnings here either, caller probably
> should not be using ctx->raddr unless we returned 0...
>
>> qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
>> HWADDR_FMT_plx " %d %d\n", __func__,
>> ret < 0 ? "refused" : "granted", address, raddr,
>> @@ -1163,20 +1159,9 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>> MMUAccessType access_type, int type,
>> int mmu_idx)
>> {
>> - bool real_mode;
>> -
>> - if (env->mmu_model == POWERPC_MMU_BOOKE) {
>> - return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
>> - } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
>> - return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
>> - mmu_idx);
>> - }
>
> This could just go in the previous patch when you split booke xlate?
Removing this uncovers the warnings so I keep it here to separate it from
the previous change. I gave up on trying to resolve these warnings and
untangle the embedded functions from mmu_ctx_t which would be needed to
move these booke functions out from this file. The other problem is that
these booke get_physical_address functions and mmu40x_get_physical_address
all use ppcemb_tlb_check which then needs to be in the same file and
static to be inlined and not run too slow but 40x is still in jumbo_xlate
so I just leave it for now and may return to it later or let somebody else
continue from here. I think this series moves forward enough for now and I
don't have more time now.
>> -
>> - real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
>> - : !FIELD_EX64(env->msr, MSR, DR);
>> - if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
>> - env->mmu_model == POWERPC_MMU_SOFT_4xx ||
>> - env->mmu_model == POWERPC_MMU_REAL)) {
>> + bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
>> + : !FIELD_EX64(env->msr, MSR, DR);
>> + if (real_mode) {
>> memset(ctx, 0, sizeof(*ctx));
>> ctx->raddr = eaddr;
>> ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>
> This still changes beahviour of MPC8xx MMU doesn't it? It's supposed
> to abort always.
I don't think it can get here because there's still an abort case in
ppc_tlb_invalidate_all() which is called from ppc_cpu_reset_hold() so it
will likely crash before it could call anything here. But if you think
it's necessary I could add a case for it in ppc_xlate() maybe.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-07 12:31 ` BALATON Zoltan
@ 2024-05-08 12:30 ` Nicholas Piggin
2024-05-08 23:33 ` BALATON Zoltan
0 siblings, 1 reply; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-08 12:30 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > What do you think about adding mmu-book3e.c instead?
>
> I have considered that but found that some functions have to be in the
> same file and declared static for the compiler to inline them otherwise I
> get worse performance. Maybe after these rearrangments it's now possible
> to move these out but as this series got a bit long already I dod not go
> through with that and left it for a follow up but I can give it a try.
It would be nice.
What host machines are you using? I'm surprised inlining is causing
so much performance unless it is something older or in-order.
Should be able to move small common things inline to headers if it's
important though, we should try to split since you've done most of
the work now.
Thanks,
Nick
>
> Thanks for the review so far, I'll try to make the changes that I
> understood and submit and updated version. I'm not sure I got some of your
> requests so that may need another round.
>
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env
2024-05-07 16:02 ` BALATON Zoltan
@ 2024-05-08 12:37 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-08 12:37 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Wed May 8, 2024 at 2:02 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This flag for split instruction/data TLBs is only set for 6xx soft TLB
> >> MMU model and not used otherwise so no need to have a separate flag
> >> for that.
> >>
> >> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> >> ---
> >> hw/ppc/pegasos2.c | 2 +-
> >> target/ppc/cpu.h | 1 -
> >> target/ppc/cpu_init.c | 19 +++++--------------
> >> target/ppc/helper_regs.c | 1 -
> >> target/ppc/mmu_common.c | 10 ++--------
> >> target/ppc/mmu_helper.c | 12 ++----------
> >> 6 files changed, 10 insertions(+), 35 deletions(-)
> >>
> >> diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
> >> index 04d6decb2b..dfc6fab180 100644
> >> --- a/hw/ppc/pegasos2.c
> >> +++ b/hw/ppc/pegasos2.c
> >> @@ -984,7 +984,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
> >> cpu->env.icache_line_size);
> >> qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
> >> cpu->env.icache_line_size);
> >> - if (cpu->env.id_tlbs) {
> >> + if (cpu->env.tlb_type == TLB_6XX) {
> >
> > Want to just add the standard comment here?
> >
> > /* 6xx has separate TLBs for instructions and data */
>
> I think that comment would be redundant here because it's clear from the
> i-tlb, d-tlb this adds so I can do without a comment in this machine if
> you don't mind. (If this was not in my machine I would not mind adding a
> comment but I'd keep this one simple.) I think comments should only be
> added for things that are not clear from code.
Yes. "Obvious" stuff just builds up until it's not.
If you make a simple inline function to test if tlb is split and it can
est TLB_6XX then you don't need the comment.
Thanks,
Nick
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()
2024-05-07 23:40 ` BALATON Zoltan
@ 2024-05-08 12:54 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-08 12:54 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Wed May 8, 2024 at 9:40 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This function is no longer called for BookE MMU model so remove parts
> >> related to it. This has uncovered a few may be used uninitialised
> >> warnings that are also fixed.
> >>
> >> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> >> ---
> >> target/ppc/mmu_common.c | 25 +++++--------------------
> >> 1 file changed, 5 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> >> index a1f98f8de4..d61c41d8c9 100644
> >> --- a/target/ppc/mmu_common.c
> >> +++ b/target/ppc/mmu_common.c
> >> @@ -684,12 +684,10 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> >> ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> >> access_type, i);
> >> if (ret != -1) {
> >> - if (ret >= 0) {
> >> - ctx->raddr = raddr;
> >> - }
> >> break;
> >> }
> >> }
> >> + ctx->raddr = raddr;
> >> qemu_log_mask(CPU_LOG_MMU,
> >> "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx
> >> " %d %d\n", __func__, ret < 0 ? "refused" : "granted",
> >> @@ -897,9 +895,6 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> >> ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
> >> access_type, mmu_idx);
> >> if (ret != -1) {
> >> - if (ret >= 0) {
> >> - ctx->raddr = raddr;
> >> - }
> >> goto found_tlb;
> >> }
> >> }
> >> @@ -907,6 +902,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> >>
> >> found_tlb:
> >>
> >> + ctx->raddr = raddr;
> >
> > Not sure about the uninitialized warnings here either, caller probably
> > should not be using ctx->raddr unless we returned 0...
> >
> >> qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
> >> HWADDR_FMT_plx " %d %d\n", __func__,
> >> ret < 0 ? "refused" : "granted", address, raddr,
> >> @@ -1163,20 +1159,9 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
> >> MMUAccessType access_type, int type,
> >> int mmu_idx)
> >> {
> >> - bool real_mode;
> >> -
> >> - if (env->mmu_model == POWERPC_MMU_BOOKE) {
> >> - return mmubooke_get_physical_address(env, ctx, eaddr, access_type);
> >> - } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> >> - return mmubooke206_get_physical_address(env, ctx, eaddr, access_type,
> >> - mmu_idx);
> >> - }
> >
> > This could just go in the previous patch when you split booke xlate?
>
> Removing this uncovers the warnings so I keep it here to separate it from
> the previous change. I gave up on trying to resolve these warnings and
> untangle the embedded functions from mmu_ctx_t which would be needed to
> move these booke functions out from this file. The other problem is that
> these booke get_physical_address functions and mmu40x_get_physical_address
> all use ppcemb_tlb_check which then needs to be in the same file and
> static to be inlined and not run too slow but 40x is still in jumbo_xlate
> so I just leave it for now and may return to it later or let somebody else
> continue from here. I think this series moves forward enough for now and I
> don't have more time now.
If you can't easily drop the path or solve the problem okay, just put
a comment or something on the zeroing and I'll take a closer look
when I merge.
>
> >> -
> >> - real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> >> - : !FIELD_EX64(env->msr, MSR, DR);
> >> - if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> >> - env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> >> - env->mmu_model == POWERPC_MMU_REAL)) {
> >> + bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> >> + : !FIELD_EX64(env->msr, MSR, DR);
> >> + if (real_mode) {
> >> memset(ctx, 0, sizeof(*ctx));
> >> ctx->raddr = eaddr;
> >> ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> >
> > This still changes beahviour of MPC8xx MMU doesn't it? It's supposed
> > to abort always.
>
> I don't think it can get here because there's still an abort case in
> ppc_tlb_invalidate_all() which is called from ppc_cpu_reset_hold() so it
> will likely crash before it could call anything here. But if you think
> it's necessary I could add a case for it in ppc_xlate() maybe.
I would rather not change it here. You can remove it with another patch.
Thanks,
Nick
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-08 12:30 ` Nicholas Piggin
@ 2024-05-08 23:33 ` BALATON Zoltan
2024-05-09 5:57 ` Nicholas Piggin
0 siblings, 1 reply; 66+ messages in thread
From: BALATON Zoltan @ 2024-05-08 23:33 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Wed, 8 May 2024, Nicholas Piggin wrote:
> On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
>> On Tue, 7 May 2024, Nicholas Piggin wrote:
>>> What do you think about adding mmu-book3e.c instead?
>>
>> I have considered that but found that some functions have to be in the
>> same file and declared static for the compiler to inline them otherwise I
>> get worse performance. Maybe after these rearrangments it's now possible
>> to move these out but as this series got a bit long already I dod not go
>> through with that and left it for a follow up but I can give it a try.
>
> It would be nice.
OK I've done that now as this also helps with some of the unint warnings
but I could not get rid of all work arounds completely.
> What host machines are you using? I'm surprised inlining is causing
> so much performance unless it is something older or in-order.
Maybe it depends more on the compiler than host. I still use gcc 10 with
default -O2 level. Some people found that -O3 and LTO may help a bit but I
test with default QEMU settings as that may be what most use.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together
2024-05-08 23:33 ` BALATON Zoltan
@ 2024-05-09 5:57 ` Nicholas Piggin
0 siblings, 0 replies; 66+ messages in thread
From: Nicholas Piggin @ 2024-05-09 5:57 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza
On Thu May 9, 2024 at 9:33 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> >> On Tue, 7 May 2024, Nicholas Piggin wrote:
> >>> What do you think about adding mmu-book3e.c instead?
> >>
> >> I have considered that but found that some functions have to be in the
> >> same file and declared static for the compiler to inline them otherwise I
> >> get worse performance. Maybe after these rearrangments it's now possible
> >> to move these out but as this series got a bit long already I dod not go
> >> through with that and left it for a follow up but I can give it a try.
> >
> > It would be nice.
>
> OK I've done that now as this also helps with some of the unint warnings
> but I could not get rid of all work arounds completely.
Great, thank you.
> > What host machines are you using? I'm surprised inlining is causing
> > so much performance unless it is something older or in-order.
>
> Maybe it depends more on the compiler than host. I still use gcc 10 with
> default -O2 level. Some people found that -O3 and LTO may help a bit but I
> test with default QEMU settings as that may be what most use.
I was thinking just the cost of call/return should not be great.
It is definitely possible for inlining to allow compiler to make
more significant optimisations.
Since you're looking closely at performance and probably nobody
else has for a while I have no problem with it if you find it
faster, mind you.
Thanks,
Nick
^ permalink raw reply [flat|nested] 66+ messages in thread
end of thread, other threads:[~2024-05-09 5:57 UTC | newest]
Thread overview: 66+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
2024-05-07 9:18 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
2024-05-07 9:19 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
2024-05-07 9:20 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
2024-05-07 9:30 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
2024-05-07 9:34 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
2024-05-07 9:36 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
2024-05-07 9:42 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
2024-05-07 9:43 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
2024-05-07 9:50 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
2024-05-07 9:58 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
2024-05-07 10:00 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
2024-05-07 10:03 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
2024-05-07 10:04 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
2024-05-07 10:05 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 10:06 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 10:11 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
2024-05-07 10:47 ` Nicholas Piggin
2024-05-07 15:31 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
2024-05-07 10:49 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
2024-05-07 11:35 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 11:51 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
2024-05-07 12:05 ` Nicholas Piggin
2024-05-07 23:40 ` BALATON Zoltan
2024-05-08 12:54 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
2024-05-07 12:15 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
2024-05-07 12:17 ` Nicholas Piggin
2024-05-07 12:31 ` BALATON Zoltan
2024-05-08 12:30 ` Nicholas Piggin
2024-05-08 23:33 ` BALATON Zoltan
2024-05-09 5:57 ` Nicholas Piggin
2024-05-07 15:54 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
2024-05-07 12:30 ` Nicholas Piggin
2024-05-07 16:02 ` BALATON Zoltan
2024-05-08 12:37 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
2024-05-07 12:40 ` Nicholas Piggin
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
2024-05-07 12:51 ` BALATON Zoltan
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