From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Richard Henderson <richard.henderson@linaro.org>,
mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
Alistair.Francis@wdc.com
Cc: peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
Date: Fri, 11 Jan 2019 14:10:29 +0100 [thread overview]
Message-ID: <b0269eb1-9fa8-449e-68ee-adbc55d15e18@mail.uni-paderborn.de> (raw)
In-Reply-To: <16797a6b-1b0b-1f83-1aef-5cc5a8ff90e6@linaro.org>
On 10/31/18 11:18 PM, Richard Henderson wrote:
>
> Surely the shri and sari functions need the same shamt >= TARGET_LONG_BITS
> check as slli. Otherwise RV32 shri should definitely produce an assert in
> tcg_gen_shri_tl.
>
> I did wonder about changing the decode of the shift functions such that only
> the top two bits of the imm are reserved for secondary parsing of the shift
> type, and the other 10 bits are passed down into trans_foo. At which point the
> TARGET_LONG_BITS check takes care of other illegalities.
>
> Which means that the parsing for slli and slliw are identical, and also that
> for the far future when RV128 is a thing, we don't have to change the parsing.
I don't quite understand this. Do you want to have one entry in the
decode file for slli and slliw?
How is the parsing of slli and slliw identical with this change? As far
as I see it, they are different at least in the opcode.
Cheers,
Bastian
next prev parent reply other threads:[~2019-01-11 13:10 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-31 13:19 [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-31 17:07 ` Richard Henderson
2018-10-31 20:14 ` Alistair Francis
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-31 20:20 ` Alistair
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-31 17:11 ` Richard Henderson
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2018-10-31 13:19 ` [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2018-10-31 17:14 ` Richard Henderson
2018-10-31 20:26 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-31 17:15 ` Richard Henderson
2018-10-31 20:29 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-31 20:30 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-31 20:46 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-31 20:38 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-31 20:49 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-31 20:50 ` Alistair
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-31 22:09 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-31 22:09 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-31 22:18 ` Richard Henderson
2019-01-11 13:10 ` Bastian Koppelmann [this message]
2019-01-11 21:00 ` Richard Henderson
2019-01-18 12:00 ` Bastian Koppelmann
2018-10-31 22:26 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-31 20:44 ` Alistair Francis
2018-10-31 22:27 ` Richard Henderson
2018-10-31 22:26 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-31 22:38 ` Richard Henderson
2018-11-01 15:59 ` Palmer Dabbelt
2018-11-05 17:00 ` Bastian Koppelmann
2018-11-07 0:56 ` Palmer Dabbelt
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-31 22:39 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2018-10-31 22:42 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2018-10-31 22:43 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2018-10-31 22:45 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2018-10-31 22:47 ` Richard Henderson
2018-10-31 13:20 ` [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2018-10-31 22:49 ` Richard Henderson
2018-11-02 8:48 ` [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree no-reply
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