From: Bui Quang Minh <minhquangbui99@gmail.com>
To: qemu-devel@nongnu.org
Cc: "David Woodhouse" <dwmw2@infradead.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Joao Martins" <joao.m.martins@oracle.com>,
"Peter Xu" <peterx@redhat.com>,
"Jason Wang" <jasowang@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH v8 0/5] Support x2APIC mode with TCG accelerator
Date: Thu, 5 Oct 2023 22:50:34 +0700 [thread overview]
Message-ID: <b05e4594-aa41-477f-9914-2835ebe9643b@gmail.com> (raw)
In-Reply-To: <20230926160637.27995-1-minhquangbui99@gmail.com>
On 9/26/23 23:06, Bui Quang Minh wrote:
> Hi everyone,
>
> This series implements x2APIC mode in userspace local APIC and the
> RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
> and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
> series, we can now boot Linux kernel into x2APIC mode with TCG accelerator
> using either Intel or AMD iommu.
>
> Testing to boot my own built Linux 6.3.0-rc2, the kernel successfully boot
> with enabled x2APIC and can enumerate CPU with APIC ID 257
>
> Using Intel IOMMU
>
> qemu/build/qemu-system-x86_64 \
> -smp 2,maxcpus=260 \
> -cpu qemu64,x2apic=on \
> -machine q35 \
> -device intel-iommu,intremap=on,eim=on \
> -device qemu64-x86_64-cpu,x2apic=on,core-id=257,socket-id=0,thread-id=0 \
> -m 2G \
> -kernel $KERNEL_DIR \
> -append "nokaslr console=ttyS0 root=/dev/sda earlyprintk=serial net.ifnames=0" \
> -drive file=$IMAGE_DIR,format=raw \
> -nographic \
> -s
>
> Using AMD IOMMU
>
> qemu/build/qemu-system-x86_64 \
> -smp 2,maxcpus=260 \
> -cpu qemu64,x2apic=on \
> -machine q35 \
> -device amd-iommu,intremap=on,xtsup=on \
> -device qemu64-x86_64-cpu,x2apic=on,core-id=257,socket-id=0,thread-id=0 \
> -m 2G \
> -kernel $KERNEL_DIR \
> -append "nokaslr console=ttyS0 root=/dev/sda earlyprintk=serial net.ifnames=0" \
> -drive file=$IMAGE_DIR,format=raw \
> -nographic \
> -s
>
> Testing the emulated userspace APIC with kvm-unit-tests, disable test
> device with this patch
>
> diff --git a/lib/x86/fwcfg.c b/lib/x86/fwcfg.c
> index 1734afb..f56fe1c 100644
> --- a/lib/x86/fwcfg.c
> +++ b/lib/x86/fwcfg.c
> @@ -27,6 +27,7 @@ static void read_cfg_override(void)
>
> if ((str = getenv("TEST_DEVICE")))
> no_test_device = !atol(str);
> + no_test_device = true;
>
> if ((str = getenv("MEMLIMIT")))
> fw_override[FW_CFG_MAX_RAM] = atol(str) * 1024 * 1024;
>
> ~ env QEMU=/home/minh/Desktop/oss/qemu/build/qemu-system-x86_64 ACCEL=tcg \
> ./run_tests.sh -v -g apic
>
> TESTNAME=apic-split TIMEOUT=90s ACCEL=tcg ./x86/run x86/apic.flat -smp 2
> -cpu qemu64,+x2apic,+tsc-deadline -machine kernel_irqchip=split FAIL
> apic-split (54 tests, 8 unexpected failures, 1 skipped)
> TESTNAME=ioapic-split TIMEOUT=90s ACCEL=tcg ./x86/run x86/ioapic.flat -smp
> 1 -cpu qemu64 -machine kernel_irqchip=split PASS ioapic-split (19 tests)
> TESTNAME=x2apic TIMEOUT=30 ACCEL=tcg ./x86/run x86/apic.flat -smp 2 -cpu
> qemu64,+x2apic,+tsc-deadline FAIL x2apic (54 tests, 8 unexpected failures,
> 1 skipped) TESTNAME=xapic TIMEOUT=60 ACCEL=tcg ./x86/run x86/apic.flat -smp
> 2 -cpu qemu64,-x2apic,+tsc-deadline -machine pit=off FAIL xapic (43 tests,
> 6 unexpected failures, 2 skipped)
>
> FAIL: apic_disable: *0xfee00030: 50014
> FAIL: apic_disable: *0xfee00080: f0
> FAIL: apic_disable: *0xfee00030: 50014
> FAIL: apic_disable: *0xfee00080: f0
> FAIL: apicbase: relocate apic
>
> These errors are because we don't disable MMIO region when switching to
> x2APIC and don't support relocate MMIO region yet. This is a problem
> because, MMIO region is the same for all CPUs, in order to support these we
> need to figure out how to allocate and manage different MMIO regions for
> each CPUs. This can be an improvement in the future.
I've tried to address these failed tests with the idea of creating
separate APIC MMIO region per CPU. I've created a working patch with
this approach and will send it in reply to this message, you can see the
detail in the patch. However, it has a big drawback, it breaks MSI
handler. With that patch, device needs to call apic_send_msi directly
instead of writing to 0xfee00000 in system memory. Furthermore, I think
APIC MMIO relocation is a very unusual use case and APIC MMIO disable is
not much important for normal system software. I'm pleased to receive
any comments on that patch.
Thank you,
Quang Minh.
next prev parent reply other threads:[~2023-10-05 15:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-26 16:06 [PATCH v8 0/5] Support x2APIC mode with TCG accelerator Bui Quang Minh
2023-09-26 16:06 ` [PATCH v8 1/5] i386/tcg: implement x2APIC registers MSR access Bui Quang Minh
2023-10-22 13:59 ` Phil Dennis-Jordan
2023-10-24 15:27 ` Bui Quang Minh
2023-09-26 16:06 ` [PATCH v8 2/5] apic: add support for x2APIC mode Bui Quang Minh
2023-09-26 16:06 ` [PATCH v8 3/5] apic, i386/tcg: add x2apic transitions Bui Quang Minh
2023-09-26 16:06 ` [PATCH v8 4/5] intel_iommu: allow Extended Interrupt Mode when using userspace APIC Bui Quang Minh
2023-09-26 16:06 ` [PATCH v8 5/5] amd_iommu: report x2APIC support to the operating system Bui Quang Minh
2023-09-26 16:23 ` [PATCH v8 0/5] Support x2APIC mode with TCG accelerator Bui Quang Minh
2023-10-04 6:51 ` Michael S. Tsirkin
2023-10-04 16:40 ` Bui Quang Minh
2023-10-04 17:05 ` Michael S. Tsirkin
2023-10-05 15:50 ` Bui Quang Minh [this message]
2023-10-05 15:52 ` [RFC PATCH] tcg, apic: create a separate root memory region for each CPU Bui Quang Minh
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