From: WANG Xuerui <i.qemu@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: git@xen0n.name, c@jia.je, gaosong@loongson.cn, yangxiaojuan@loongson.cn
Subject: Re: [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store
Date: Sun, 1 Oct 2023 03:04:03 +0800 [thread overview]
Message-ID: <b082d345-72e0-44a6-a303-f2291999726b@xen0n.name> (raw)
In-Reply-To: <b9704f72-e4de-74e4-9b10-8ba14cea3d2d@linaro.org>
On 9/30/23 10:13, Richard Henderson wrote:
> Ping.
>
> r~
>
> On 9/16/23 15:01, Richard Henderson wrote:
>> For tcg generated code, use new registers with load so that we never
>> overlap the input address, so that we can simplify address build for
>> 64-bit user-only.
>>
>> For tcg out-of-line code, implement the host/ headers to for atomic
>> 128-bit
>> load and store, reducing the cases for which we must raise EXCP_ATOMIC.
>>
>>
>> r~
>>
>> Based-on: 20230916171223.521545-1-richard.henderson@linaro.org
>> ("[PULL v2 00/39] tcg patch queue")
>>
>> Richard Henderson (7):
>> tcg: Add C_N2_I1
>> tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
>> util: Add cpuinfo for loongarch64
>> tcg/loongarch64: Use cpuinfo.h
>> host/include/loongarch64: Add atomic16 load and store
>> accel/tcg: Remove redundant case in store_atom_16
>> accel/tcg: Fix condition for store_atom_insert_al16
>>
>> .../include/loongarch64/host/atomic128-ldst.h | 52 +++++++++++++++++++
>> host/include/loongarch64/host/cpuinfo.h | 21 ++++++++
>> .../loongarch64/host/load-extract-al16-al8.h | 39 ++++++++++++++
>> .../loongarch64/host/store-insert-al16.h | 12 +++++
>> tcg/loongarch64/tcg-target-con-set.h | 2 +-
>> tcg/loongarch64/tcg-target.h | 8 +--
>> accel/tcg/cputlb.c | 2 +-
>> tcg/tcg.c | 5 ++
>> util/cpuinfo-loongarch.c | 35 +++++++++++++
>> accel/tcg/ldst_atomicity.c.inc | 14 ++---
>> tcg/loongarch64/tcg-target.c.inc | 25 +++++----
>> util/meson.build | 2 +
>> 12 files changed, 189 insertions(+), 28 deletions(-)
>> create mode 100644 host/include/loongarch64/host/atomic128-ldst.h
>> create mode 100644 host/include/loongarch64/host/cpuinfo.h
>> create mode 100644
>> host/include/loongarch64/host/load-extract-al16-al8.h
>> create mode 100644 host/include/loongarch64/host/store-insert-al16.h
>> create mode 100644 util/cpuinfo-loongarch.c
Sorry for the delay; I've skimmed through the series and tested on
Loongson 3C5000L hardware, so
Reviewed-by: WANG Xuerui <git@xen0n.name>
prev parent reply other threads:[~2023-09-30 19:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-16 22:01 [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-16 22:01 ` [PATCH 1/7] tcg: Add C_N2_I1 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 2/7] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 3/7] util: Add cpuinfo for loongarch64 Richard Henderson
2023-09-30 11:40 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 4/7] tcg/loongarch64: Use cpuinfo.h Richard Henderson
2023-09-30 11:41 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 5/7] host/include/loongarch64: Add atomic16 load and store Richard Henderson
2023-09-16 22:01 ` [PATCH 6/7] accel/tcg: Remove redundant case in store_atom_16 Richard Henderson
2023-09-16 22:01 ` [PATCH 7/7] accel/tcg: Fix condition for store_atom_insert_al16 Richard Henderson
2023-09-30 2:13 ` [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-30 19:04 ` WANG Xuerui [this message]
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