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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id w3-20020a379403000000b006bb29d932e1sm12365822qkd.105.2023.02.14.10.36.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Feb 2023 10:36:36 -0800 (PST) Message-ID: Date: Tue, 14 Feb 2023 19:36:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH 2/2] hw/arm/smmu-common: Fix TTB1 handling Content-Language: en-US To: Jean-Philippe Brucker Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, ola.hugosson@arm.com References: <20230210163731.970130-1-jean-philippe@linaro.org> <20230210163731.970130-3-jean-philippe@linaro.org> <1964d20f-e18b-5875-914b-16f2f3acee37@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.35, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/14/23 17:46, Jean-Philippe Brucker wrote: > On Mon, Feb 13, 2023 at 05:30:03PM +0100, Eric Auger wrote: >> Hi Jean, >> >> On 2/10/23 17:37, Jean-Philippe Brucker wrote: >>> Addresses targeting the second translation table (TTB1) in the SMMU have >>> all upper bits set (except for the top byte when TBI is enabled). Fix >>> the TTB1 check. >>> >>> Reported-by: Ola Hugosson >>> Signed-off-by: Jean-Philippe Brucker >>> --- >>> hw/arm/smmu-common.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c >>> index 2b8c67b9a1..0a5a60ca1e 100644 >>> --- a/hw/arm/smmu-common.c >>> +++ b/hw/arm/smmu-common.c >>> @@ -249,7 +249,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) >>> /* there is a ttbr0 region and we are in it (high bits all zero) */ >>> return &cfg->tt[0]; >>> } else if (cfg->tt[1].tsz && >>> - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { >>> + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { >>> /* there is a ttbr1 region and we are in it (high bits all one) */ >>> return &cfg->tt[1]; >>> } else if (!cfg->tt[0].tsz) { >> Reviewed-by: Eric Auger >> >> While reading the spec again, I noticed we do not support VAX. Is it >> something that we would need to support? > I guess it would be needed to support sharing page tables with the CPU, if > the CPU supports and the OS uses FEAT_LVA. But in order to share the > stage-1, Linux would need more complex features as well (ATS+PRI/Stall, > PASID). > > For a private DMA address space, I think 48 bits of VA is already plenty. OK thanks! Eric > > Thanks, > Jean >