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Thu, 10 Jul 2025 10:07:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEeoL/uN8FEUvl/TbDZCCkQZPIolroXIeGZAKOpWfqCMc2WogtFMXydeNnWK3tTXPuufZnXuw== X-Received: by 2002:a17:90b:1dc2:b0:311:fc8b:31b5 with SMTP id 98e67ed59e1d1-31c4cb85d2dmr462732a91.14.1752167235712; Thu, 10 Jul 2025 10:07:15 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31c3eb7e9ecsm2826856a91.42.2025.07.10.10.07.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jul 2025 10:07:15 -0700 (PDT) Message-ID: Date: Thu, 10 Jul 2025 13:07:11 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/20] hw/pci: Introduce pci_device_get_viommu_cap() Content-Language: en-US From: Donald Dutile To: Shameerali Kolothum Thodi , Nicolin Chen Cc: Zhenzhong Duan , "qemu-devel@nongnu.org" , "alex.williamson@redhat.com" , "clg@redhat.com" , "eric.auger@redhat.com" , "mst@redhat.com" , "jasowang@redhat.com" , "peterx@redhat.com" , "jgg@nvidia.com" , "joao.m.martins@oracle.com" , "clement.mathieu--drif@eviden.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "chao.p.peng@intel.com" References: <20250708110601.633308-1-zhenzhong.duan@intel.com> <20250708110601.633308-3-zhenzhong.duan@intel.com> <01584206-e2c0-4881-aaf5-d6c552a30873@redhat.com> <5542e55f-5cd9-40f8-bb45-fe6d851140b1@redhat.com> In-Reply-To: <5542e55f-5cd9-40f8-bb45-fe6d851140b1@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=ddutile@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org oops, inadvertently hit send before I could add reply... apologies... reply below... On 7/10/25 1:01 PM, Donald Dutile wrote: > > > On 7/10/25 4:11 AM, Shameerali Kolothum Thodi wrote: >> >> >>> -----Original Message----- >>> From: Nicolin Chen >>> Sent: Wednesday, July 9, 2025 8:20 PM >>> To: Donald Dutile >>> Cc: Zhenzhong Duan ; qemu- >>> devel@nongnu.org; alex.williamson@redhat.com; clg@redhat.com; >>> eric.auger@redhat.com; mst@redhat.com; jasowang@redhat.com; >>> peterx@redhat.com; jgg@nvidia.com; Shameerali Kolothum Thodi >>> ; joao.m.martins@oracle.com; >>> clement.mathieu--drif@eviden.com; kevin.tian@intel.com; >>> yi.l.liu@intel.com; chao.p.peng@intel.com >>> Subject: Re: [PATCH v3 02/20] hw/pci: Introduce >>> pci_device_get_viommu_cap() >>> >>> On Wed, Jul 09, 2025 at 01:55:46PM -0400, Donald Dutile wrote: >>>>>> +enum { >>>>>> +    VIOMMU_CAP_STAGE1 = BIT_ULL(0),  /* stage1 page table >>> supported */ >>>>>> +}; >>>>> >>>>> Thanks for this work. I am happy to see that we can share the >>>>> common code that allocates a NESTING_PARENT in the core using >>>>> this flag. >>>>> >>>>> Yet on ARM, a STAGE1 page table isn't always a nested S1, the >>>>> hardware accelerated one. More often, it can be just a regular >>>>> 1-stage translation table via emulated translation code and an >>>>> emulated iotlb. >>>>> >>>> Because the user-created smmuv3 started as 'accelerated smmuv3', >>>> and had been 'de-accelerated' to simply 'user created smmuv3', >>>> I'm looking for some clarification in the above statement/request. >>>> >>>> Is the above suppose to reflect that a nested IOMMU has some hw- >>> acceleration >>>> in its Stage1 implementation? >>>> If so, then call it that: STAGE1_ACCEL. >>>> If it's suppose to represent that an IOMMU has nested/2-stage support, >>>> then the above is a valid cap;  -but-, having a nested/2-stage support >>> IOMMU >>>> doesn't necessarily mean its accelerated. >>> >>> Well, there are an emulated "nested" mode and an hw-accelerated >>> "nested" mode in the smmuv3 code, so we had to choose something >>> like "accel" over "nested". >>> >>> Here, on the other hand, I think the core using this CAP would >>> unlikely care about an emulated "nested" mode in the individual >>> vIOMMU.. >>> >>> So I suggested: >>>       /* hardware-accelerated nested stage-1 page table support */ >>>      VIOMMU_CAP_NESTED_S1 = BIT_ULL(0), >>> >>> which it should be clear IMHO. >>> >>> If not, maybe go a bit further like "VIOMMU_CAP_HW_NESTED_S1"? >> >> I am not sure the _S1 part makes much sense in ARM case. It doesn't matter >> whether the Guest SMMUv3 is configured in s1/s2 or nested for this CAP. >> With the new SMMUv3 dev support, the user can pretty much specify, >> >> -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.1,accel=on,stage={stage1|stage2|nested} >> >> And I think it will work with a host SMMUv3 nested configuration in all the >> above cases. Unless I am missing something and we need to restrict its >> use with stage=stage1 only. >> >> Thanks, >> Shameer >> Shameer, I didn't think of these config options this way... so is this CAP always 0 for smmuv3's associated VIOMMU? or ... should intel-iommu follow this same/smmuv3 config option(s) and avoid this VIOMMU CAP req. ? - Don