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Tsirkin" , Manos Pitsidianakis , Junjie Mao , =?UTF-8?Q?Alex_Benn=C3=A9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org References: <20241205060714.256270-1-zhao1.liu@intel.com> <20241205060714.256270-12-zhao1.liu@intel.com> From: Paolo Bonzini Content-Language: en-US Autocrypt: addr=pbonzini@redhat.com; keydata= xsEhBFRCcBIBDqDGsz4K0zZun3jh+U6Z9wNGLKQ0kSFyjN38gMqU1SfP+TUNQepFHb/Gc0E2 CxXPkIBTvYY+ZPkoTh5xF9oS1jqI8iRLzouzF8yXs3QjQIZ2SfuCxSVwlV65jotcjD2FTN04 hVopm9llFijNZpVIOGUTqzM4U55sdsCcZUluWM6x4HSOdw5F5Utxfp1wOjD/v92Lrax0hjiX DResHSt48q+8FrZzY+AUbkUS+Jm34qjswdrgsC5uxeVcLkBgWLmov2kMaMROT0YmFY6A3m1S P/kXmHDXxhe23gKb3dgwxUTpENDBGcfEzrzilWueOeUWiOcWuFOed/C3SyijBx3Av/lbCsHU Vx6pMycNTdzU1BuAroB+Y3mNEuW56Yd44jlInzG2UOwt9XjjdKkJZ1g0P9dwptwLEgTEd3Fo UdhAQyRXGYO8oROiuh+RZ1lXp6AQ4ZjoyH8WLfTLf5g1EKCTc4C1sy1vQSdzIRu3rBIjAvnC tGZADei1IExLqB3uzXKzZ1BZ+Z8hnt2og9hb7H0y8diYfEk2w3R7wEr+Ehk5NQsT2MPI2QBd wEv1/Aj1DgUHZAHzG1QN9S8wNWQ6K9DqHZTBnI1hUlkp22zCSHK/6FwUCuYp1zcAEQEAAc0j UGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT7CwU0EEwECACMFAlRCcBICGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRB+FRAMzTZpsbceDp9IIN6BIA0Ol7MoB15E 11kRz/ewzryFY54tQlMnd4xxfH8MTQ/mm9I482YoSwPMdcWFAKnUX6Yo30tbLiNB8hzaHeRj jx12K+ptqYbg+cevgOtbLAlL9kNgLLcsGqC2829jBCUTVeMSZDrzS97ole/YEez2qFpPnTV0 VrRWClWVfYh+JfzpXmgyhbkuwUxNFk421s4Ajp3d8nPPFUGgBG5HOxzkAm7xb1cjAuJ+oi/K CHfkuN+fLZl/u3E/fw7vvOESApLU5o0icVXeakfSz0LsygEnekDbxPnE5af/9FEkXJD5EoYG SEahaEtgNrR4qsyxyAGYgZlS70vkSSYJ+iT2rrwEiDlo31MzRo6Ba2FfHBSJ7lcYdPT7bbk9 AO3hlNMhNdUhoQv7M5HsnqZ6unvSHOKmReNaS9egAGdRN0/GPDWr9wroyJ65ZNQsHl9nXBqE AukZNr5oJO5vxrYiAuuTSd6UI/xFkjtkzltG3mw5ao2bBpk/V/YuePrJsnPFHG7NhizrxttB nTuOSCMo45pfHQ+XYd5K1+Cv/NzZFNWscm5htJ0HznY+oOsZvHTyGz3v91pn51dkRYN0otqr bQ4tlFFuVjArBZcapSIe6NV8C4cEiSTOwE0EVEJx7gEIAMeHcVzuv2bp9HlWDp6+RkZe+vtl KwAHplb/WH59j2wyG8V6i33+6MlSSJMOFnYUCCL77bucx9uImI5nX24PIlqT+zasVEEVGSRF m8dgkcJDB7Tps0IkNrUi4yof3B3shR+vMY3i3Ip0e41zKx0CvlAhMOo6otaHmcxr35sWq1Jk tLkbn3wG+fPQCVudJJECvVQ//UAthSSEklA50QtD2sBkmQ14ZryEyTHQ+E42K3j2IUmOLriF dNr9NvE1QGmGyIcbw2NIVEBOK/GWxkS5+dmxM2iD4Jdaf2nSn3jlHjEXoPwpMs0KZsgdU0pP JQzMUMwmB1wM8JxovFlPYrhNT9MAEQEAAcLBMwQYAQIACQUCVEJx7gIbDAAKCRB+FRAMzTZp sadRDqCctLmYICZu4GSnie4lKXl+HqlLanpVMOoFNnWs9oRP47MbE2wv8OaYh5pNR9VVgyhD OG0AU7oidG36OeUlrFDTfnPYYSF/mPCxHttosyt8O5kabxnIPv2URuAxDByz+iVbL+RjKaGM GDph56ZTswlx75nZVtIukqzLAQ5fa8OALSGum0cFi4ptZUOhDNz1onz61klD6z3MODi0sBZN Aj6guB2L/+2ZwElZEeRBERRd/uommlYuToAXfNRdUwrwl9gRMiA0WSyTb190zneRRDfpSK5d usXnM/O+kr3Dm+Ui+UioPf6wgbn3T0o6I5BhVhs4h4hWmIW7iNhPjX1iybXfmb1gAFfjtHfL xRUr64svXpyfJMScIQtBAm0ihWPltXkyITA92ngCmPdHa6M1hMh4RDX+Jf1fiWubzp1voAg0 JBrdmNZSQDz0iKmSrx8xkoXYfA3bgtFN8WJH2xgFL28XnqY4M6dLhJwV3z08tPSRqYFm4NMP dRsn0/7oymhneL8RthIvjDDQ5ktUjMe8LtHr70OZE/TT88qvEdhiIVUogHdo4qBrk41+gGQh b906Dudw5YhTJFU3nC6bbF2nrLlB4C/XSiH76ZvqzV0Z/cAMBo5NF/w= In-Reply-To: <20241205060714.256270-12-zhao1.liu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/5/24 07:07, Zhao Liu wrote: > Add the HPETTimer and HPETState (HPET timer block), along with their > basic methods and register definitions. > > This is in preparation for supporting the QAPI interfaces. > > Note, wrap all items in HPETState that may be changed in the callback > called by C code into the BqlCell/BqlRefCell. > > Signed-off-by: Zhao Liu > --- > rust/hw/timer/hpet/src/hpet.rs | 638 +++++++++++++++++++++++++++++++++ > rust/hw/timer/hpet/src/lib.rs | 1 + > rust/wrapper.h | 1 + > 3 files changed, 640 insertions(+) > create mode 100644 rust/hw/timer/hpet/src/hpet.rs > > diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs > new file mode 100644 > index 000000000000..9550d8fe438a > --- /dev/null > +++ b/rust/hw/timer/hpet/src/hpet.rs > @@ -0,0 +1,638 @@ > +// Copyright (C) 2024 Intel Corporation. > +// Author(s): Zhao Liu > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#![allow(dead_code)] > + > +use core::ptr::{null_mut, NonNull}; > +use std::os::raw::c_int; > + > +use qemu_api::{ > + bindings::*, Let's avoid bindings::*. > + self.qemu_timer = Box::new(HPETState::timer_new_ns( Oh! I noticed now that while your API is called timer_new_ns, it is actually the same as timer_init_full. Let's call it init_full() then. > + fn get_state_ref(&self) -> &HPETState { > + // SAFETY: > + // the pointer is convertible to a reference > + unsafe { self.state.unwrap().as_ref() } > + } > + > + fn get_state_mut(&mut self) -> &mut HPETState { > + // SAFETY: > + // the pointer is convertible to a reference > + unsafe { self.state.unwrap().as_mut() } > + } You should not need get_state_mut(), which also has the advantage of shortening get_state_ref() to get_state(). > + > + fn is_int_active(&self) -> bool { > + self.get_state_ref().int_status.get() & (1 << self.index) != 0 > + } > + > + fn is_fsb_route_enabled(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_FSB_ENABLE_SHIFT != 0 > + } > + > + fn is_periodic(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_PERIODIC_SHIFT != 0 > + } > + > + fn is_int_enabled(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_INT_ENABLE_SHIFT != 0 > + } > + > + fn is_32bit_mod(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_32BIT_SHIFT != 0 > + } > + > + fn is_valset_enabled(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_SETVAL_SHIFT != 0 > + } > + > + fn clear_valset(&mut self) { > + self.config &= !(1 << HPET_TN_CFG_SETVAL_SHIFT); > + } > + > + /// True if timer interrupt is level triggered; otherwise, edge triggered. > + fn is_int_level_triggered(&self) -> bool { > + self.config & 1 << HPET_TN_CFG_INT_TYPE_SHIFT != 0 > + } PL011 is using bilge here. I think it's fair to show the two ways to do it. If we have devices showing two different things: - PL011 shows higher-level abstractions for registers - HPET has a good approach to interior mutability from the beginning Then it gives a clearer view of the options. > + fn update_int_status(&mut self, set: bool) -> &mut Self { > + let mask: u64 = 1 << self.index; > + > + if set && self.is_int_level_triggered() { > + // If Timer N Interrupt Enable bit is 0, "the timer will > + // still operate and generate appropriate status bits, but > + // will not cause an interrupt" > + *self.get_state_mut().int_status.get_mut() |= mask; > + } else { > + *self.get_state_mut().int_status.get_mut() &= !mask; > + } > + self > + } See remarks elsewhere on update_int_status(), and how it uses get_state_mut() and get_mut(). > + unsafe { > + address_space_stl_le( > + &mut address_space_memory, > + self.fsb >> 32, // Timer N FSB int addr > + self.fsb as u32, // Timer N FSB int value, truncate! > + *MEMTXATTRS_UNSPECIFIED, > + null_mut(), > + ); > + } This is the only use of unsafe, whic is not bad at all. Not urgent, but we should think about the AddressSpace bindings, and whether it makes sense to use (or steal APIs from) rust-vmm's vm-memory. > + fn arm_timer(&mut self, tick: u64) { > + let mut ns = self.get_state_ref().get_ns(tick); > + > + // Clamp period to reasonable min value (1 us) > + if self.is_periodic() && ns - self.last < 1000 { > + ns = self.last + 1000; > + } > + > + self.last = ns; > + self.qemu_timer.as_mut().timer_mod(self.last); > + } No as_mut(), timer_mod is thread safe. timer_mod() need to take &self. > + fn del_timer(&mut self) { > + self.qemu_timer.as_mut().timer_del(); Same as above. > +#[derive(Debug)] > +pub struct HPETTimerInstance(BqlRefCell); > + > +impl HPETTimerInstance { > + fn timer_handler(timer: &mut HPETTimerInstance) { > + timer.0.borrow_mut().callback() > + } > +} Also not "&mut" - you don't need it, as "timer.0" is only used to borrow from the BqlRefCell. Also with a more refined timer abstraction this doesn't need HPETTimerInstance, it can probably be a global function like fn timer_handler(timer_cell: &BqlRefCell) { timer_cell.borrow_mut().callback() } > + /// General Capabilities and ID Register > + capability: BqlCell, > + /// General Configuration Register > + config: BqlCell, > + /// General Interrupt Status Register > + int_status: BqlCell, > + /// Main Counter Value Register > + counter: BqlCell, > + > + /// Internal state > + > + /// Capabilities that QEMU HPET supports. > + /// bit 0: MSI (or FSB) support. > + pub(crate) flags: BqlCell, flags doesn't need to be a cell (it's just a property). I'll send a patch for the C code. > + /// Offset of main counter relative to qemu clock. > + hpet_offset: BqlCell, > + pub(crate) hpet_offset_saved: bool, > + > + irqs: [InterruptSource; HPET_NUM_IRQ_ROUTES], > + rtc_irq_level: BqlCell, > + pit_enabled: InterruptSource, > + > + /// Interrupt Routing Capability. > + /// This field indicates to which interrupts in the I/O (x) APIC > + /// the timers' interrupt can be routed, and is encoded in the > + /// bits 32:64 of timer N's config register: > + pub(crate) int_route_cap: u32, > + > + /// HPET timer array managed by this timer block. > + timer: [HPETTimerInstance; HPET_MAX_TIMERS], > + pub(crate) num_timers: BqlCell, Ah, this needs to be a BqlCell because it can be clamped to MIN_TIMERS..MAX_TIMERS by realize. Fair enough. > + /// Instance id (HPET timer block ID). > + hpet_id: BqlCell, > +} > + Like flags this does not need to be a cell. Paolo