From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE
Date: Fri, 31 Jan 2020 12:13:25 -0800 [thread overview]
Message-ID: <b109bbe1-50a5-65fd-d656-337482de7f85@linaro.org> (raw)
In-Reply-To: <CAFEAcA8bX4h1hjOaRv7n0wH+F+2QAVjx4wPBXCdk+RbGW0g6Sw@mail.gmail.com>
On 1/31/20 5:06 AM, Peter Maydell wrote:
> On Wed, 29 Jan 2020 at 23:56, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/cpu.h | 7 -------
>> target/arm/helper.c | 6 +++++-
>> 2 files changed, 5 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index 0477cef1ea..239c9eb783 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -1417,13 +1417,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
>> #define HCR_ATA (1ULL << 56)
>> #define HCR_DCT (1ULL << 57)
>>
>> -/*
>> - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to
>> - * HCR_MASK and then clear it again if the feature bit is not set in
>> - * hcr_write().
>> - */
>> -#define HCR_MASK ((1ULL << 34) - 1)
>> -
>> #define SCR_NS (1U << 0)
>> #define SCR_IRQ (1U << 1)
>> #define SCR_FIQ (1U << 2)
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index 19a57a17da..f5ce05fdf3 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
>> static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
>> {
>> ARMCPU *cpu = env_archcpu(env);
>> - uint64_t valid_mask = HCR_MASK;
>> + /* Begin with bits defined in base ARMv8.0. */
>> + uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
>>
>> if (arm_feature(env, ARM_FEATURE_EL3)) {
>> valid_mask &= ~HCR_HCD;
>> @@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
>> */
>> valid_mask &= ~HCR_TSC;
>> }
>> + if (cpu_isar_feature(aa64_vh, cpu)) {
>> + valid_mask |= HCR_E2H;
>> + }
>> if (cpu_isar_feature(aa64_lor, cpu)) {
>> valid_mask |= HCR_TLOR;
>> }
>
> Should HCR_E2H be in the list of bits for which we do
> a tlb_flush () in hcr_write()? (Currently we do this for
> VM, PTW and DC.) Given some of the later TLB-flushing
> changes have code that is "we only need to flush these
> TLB indexes when this register is written if E2H==1",
> it makes it easier to be sure we have the right behaviour
> if we don't need to think through scenarios of "write
> to the register, then set E2H==1"...
I don't think so, because when E2H changes, we change mmu_idx entirely.
Between E2 and E20_2 for el2, and (if TGE is also set) E10_0 and E20_0 for el0.
r~
next prev parent reply other threads:[~2020-01-31 20:14 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-29 23:55 [PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-01-29 23:55 ` [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-01-31 13:06 ` Peter Maydell
2020-01-31 20:13 ` Richard Henderson [this message]
2020-01-29 23:55 ` [PATCH v5 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-01-29 23:55 ` [PATCH v5 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-01-29 23:55 ` [PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-01-29 23:55 ` [PATCH v5 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-01-29 23:55 ` [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-01-29 23:55 ` [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-01-29 23:55 ` [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-01-29 23:55 ` [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-01-29 23:55 ` [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-01-29 23:55 ` [PATCH v5 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-01-29 23:55 ` [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-01-29 23:55 ` [PATCH v5 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-01-31 13:31 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 29/41] target/arm: Add VHE timer " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-01-31 13:11 ` Peter Maydell
2020-01-31 20:19 ` Richard Henderson
2020-01-29 23:56 ` [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-01-31 13:21 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-01-29 23:56 ` [PATCH v5 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-01-29 23:56 ` [PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-01-29 23:56 ` [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
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