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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r11sm1816138pgi.9.2020.01.31.12.13.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 31 Jan 2020 12:13:27 -0800 (PST) Subject: Re: [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE To: Peter Maydell References: <20200129235614.29829-1-richard.henderson@linaro.org> <20200129235614.29829-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 31 Jan 2020 12:13:25 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/31/20 5:06 AM, Peter Maydell wrote: > On Wed, 29 Jan 2020 at 23:56, Richard Henderson > wrote: >> >> Reviewed-by: Alex Bennée >> Signed-off-by: Richard Henderson >> --- >> target/arm/cpu.h | 7 ------- >> target/arm/helper.c | 6 +++++- >> 2 files changed, 5 insertions(+), 8 deletions(-) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index 0477cef1ea..239c9eb783 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -1417,13 +1417,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) >> #define HCR_ATA (1ULL << 56) >> #define HCR_DCT (1ULL << 57) >> >> -/* >> - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to >> - * HCR_MASK and then clear it again if the feature bit is not set in >> - * hcr_write(). >> - */ >> -#define HCR_MASK ((1ULL << 34) - 1) >> - >> #define SCR_NS (1U << 0) >> #define SCR_IRQ (1U << 1) >> #define SCR_FIQ (1U << 2) >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 19a57a17da..f5ce05fdf3 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { >> static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) >> { >> ARMCPU *cpu = env_archcpu(env); >> - uint64_t valid_mask = HCR_MASK; >> + /* Begin with bits defined in base ARMv8.0. */ >> + uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); >> >> if (arm_feature(env, ARM_FEATURE_EL3)) { >> valid_mask &= ~HCR_HCD; >> @@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) >> */ >> valid_mask &= ~HCR_TSC; >> } >> + if (cpu_isar_feature(aa64_vh, cpu)) { >> + valid_mask |= HCR_E2H; >> + } >> if (cpu_isar_feature(aa64_lor, cpu)) { >> valid_mask |= HCR_TLOR; >> } > > Should HCR_E2H be in the list of bits for which we do > a tlb_flush () in hcr_write()? (Currently we do this for > VM, PTW and DC.) Given some of the later TLB-flushing > changes have code that is "we only need to flush these > TLB indexes when this register is written if E2H==1", > it makes it easier to be sure we have the right behaviour > if we don't need to think through scenarios of "write > to the register, then set E2H==1"... I don't think so, because when E2H changes, we change mmu_idx entirely. Between E2 and E20_2 for el2, and (if TGE is also set) E10_0 and E20_0 for el0. r~