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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c445100b003c64c186206sm16973538wmn.16.2022.11.28.10.20.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Nov 2022 10:20:00 -0800 (PST) Message-ID: Date: Mon, 28 Nov 2022 19:19:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH for-8.0 2/9] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20221109161444.3397405-1-peter.maydell@linaro.org> <20221109161444.3397405-3-peter.maydell@linaro.org> From: Eric Auger In-Reply-To: <20221109161444.3397405-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eauger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.257, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 11/9/22 17:14, Peter Maydell wrote: > Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy > reset method doesn't do anything that's invalid in the hold phase, so > the conversion only requires changing it to a hold phase method, and > using the 3-phase versions of the "save the parent reset method and > chain to it" code. > > Signed-off-by: Peter Maydell Reviewed-by: Eric Auger Eric > --- > include/hw/arm/smmuv3.h | 2 +- > hw/arm/smmuv3.c | 12 ++++++++---- > 2 files changed, 9 insertions(+), 5 deletions(-) > > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index c641e60735e..f1921fdf9e7 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -77,7 +77,7 @@ struct SMMUv3Class { > /*< public >*/ > > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > }; > > #define TYPE_ARM_SMMUV3 "arm-smmuv3" > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index daa80e9c7b6..955b89c8d59 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1431,12 +1431,14 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) > } > } > > -static void smmu_reset(DeviceState *dev) > +static void smmu_reset_hold(Object *obj) > { > - SMMUv3State *s = ARM_SMMUV3(dev); > + SMMUv3State *s = ARM_SMMUV3(obj); > SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); > > - c->parent_reset(dev); > + if (c->parent_phases.hold) { > + c->parent_phases.hold(obj); > + } > > smmuv3_init_regs(s); > } > @@ -1520,10 +1522,12 @@ static void smmuv3_instance_init(Object *obj) > static void smmuv3_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > SMMUv3Class *c = ARM_SMMUV3_CLASS(klass); > > dc->vmsd = &vmstate_smmuv3; > - device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset); > + resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL, > + &c->parent_phases); > c->parent_realize = dc->realize; > dc->realize = smmu_realize; > }