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Mon, 15 Sep 2025 12:45:06 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32dd98b438esm15321766a91.14.2025.09.15.12.45.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Sep 2025 12:45:06 -0700 (PDT) Message-ID: Date: Mon, 15 Sep 2025 12:45:04 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 50/84] target/arm: Expand pstate to 64 bits To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Pierrick Bouvier References: <20250830054128.448363-1-richard.henderson@linaro.org> <20250830054128.448363-51-richard.henderson@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/8/25 08:57, Peter Maydell wrote: >> +static int get_pstate64_1(QEMUFile *f, void *opaque, size_t size, >> + const VMStateField *field) > > Why the _1 suffix ? Symbol conflict: static const VMStateInfo vmstate_pstate64_1 = { ... static const VMStateDescription vmstate_pstate64 = { The get/set_pstate64_1 symbols are named to match usage. Naming suggestions welcome. :-) > I note that there is actually a defined bit above 32 > in the SPSR_ELx format for exceptions taken from > AArch32 to AArch64: PPEND, used with FEAT_SEBEP. That > suggests we should probably at least consider handling > 64-bit AArch32 "CPSR" values, though FEAT_SEBEP in > particular may be out of scope for us. > > Incidentally I think we are not correctly migrating > PSTATE.SS when in AArch32 -- we will migrate the CPSR > via cpsr_read() / cpsr_write(), but that view doesn't have > the PSTATE.SS bit in it. Possibly these things could > be addressed at the same time, so we have a subsection > for 64-bit pstate/cpsr, and its save/load uses > cpsr_read_for_spsr_elx() (and a corresponding _write_ > that we don't have yet) when AArch32, and the .needed > function is "if top 32 bits not all zero, or PSTATE_SS bit > is set". Good catch. I'll have a look at this. r~