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Mon, 28 Jun 2021 09:54:27 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id pj4sm44583pjb.18.2021.06.28.09.54.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jun 2021 09:54:27 -0700 (PDT) Subject: Re: [PATCH 15/18] target/arm: Implement MVE long shifts by immediate To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210628135835.6690-1-peter.maydell@linaro.org> <20210628135835.6690-16-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 28 Jun 2021 09:54:25 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210628135835.6690-16-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/28/21 6:58 AM, Peter Maydell wrote: > { > + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS > + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE > + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that > + # they explicitly call unallocated_encoding() for cases that must UNDEF > + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting > + # the rest fall through (where ORR_rrri and MOV_rxri will end up > + # handling them as r13 and r15 accesses with the same semantics as A32). > + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri > + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri > + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri > + > + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri > + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri > + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri > + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri > + Could perhaps usefully be nested under [ ]. Either way, Reviewed-by: Richard Henderson r~