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[88.29.180.98]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d60cf93cb2sm14261737f8f.12.2025.09.03.03.13.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 03:13:49 -0700 (PDT) Message-ID: Date: Wed, 3 Sep 2025 12:13:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 15/24] target/arm/hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , qemu-arm@nongnu.org, Mohamed Mediouni , Peter Maydell , Mads Ynddal , Phil Dennis-Jordan , Stefan Hajnoczi , Cameron Esfahani , Roman Bolshakov , Paolo Bonzini References: <20250903100702.16726-1-philmd@linaro.org> <20250903100702.16726-16-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250903100702.16726-16-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/9/25 12:06, Philippe Mathieu-Daudé wrote: > From: Mohamed Mediouni > > Creating a vCPU locks out APIs such as hv_gic_create(). > > As a result, switch to using the hv_vcpu_config_get_feature_reg interface. > > Besides, all the following methods must be run on a vCPU thread: > > - hv_vcpu_create() > - hv_vcpu_get_sys_reg() > - hv_vcpu_destroy() > > Signed-off-by: Mohamed Mediouni > Reviewed-by: Philippe Mathieu-Daudé > Tested-by: Philippe Mathieu-Daudé > Message-ID: <20250808070137.48716-3-mohamed@unpredictable.fr> > [PMD: Release config calling os_release()] > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/hvf/hvf.c | 36 +++++++++++++++--------------------- > 1 file changed, 15 insertions(+), 21 deletions(-) > > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > index 3039c0987dc..fd209d23c1e 100644 > --- a/target/arm/hvf/hvf.c > +++ b/target/arm/hvf/hvf.c > @@ -869,24 +869,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > { > ARMISARegisters host_isar = {}; > const struct isar_regs { > - int reg; > + hv_feature_reg_t reg; > uint64_t *val; > } regs[] = { > - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] }, > /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ > - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] }, > - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] }, > + { HV_FEATURE_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] }, > /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ > + { HV_FEATURE_REG_CTR_EL0, &host_isar.idregs[CTR_EL0_IDX] }, > + { HV_FEATURE_REG_CLIDR_EL1, &host_isar.idregs[CLIDR_EL1_IDX] }, I'd rather add the 2 last ones in a distinct patch, keeping this one as a simple API conversion. > }; > - hv_vcpu_t fd; > hv_return_t r = HV_SUCCESS; > - hv_vcpu_exit_t *exit; > + hv_vcpu_config_t config = hv_vcpu_config_create(); > uint64_t t; > int i; > > @@ -897,17 +898,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > (1ULL << ARM_FEATURE_PMU) | > (1ULL << ARM_FEATURE_GENERIC_TIMER); > > - /* We set up a small vcpu to extract host registers */ > - > - if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { > - return false; > - } > - > for (i = 0; i < ARRAY_SIZE(regs); i++) { > - r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); > + r |= hv_vcpu_config_get_feature_reg(config, regs[i].reg, regs[i].val); > } > - r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); > - r |= hv_vcpu_destroy(fd); > + os_release(config); > > /* > * Hardcode MIDR because Apple deliberately doesn't expose a divergent