From: Richard Henderson <richard.henderson@linaro.org>
To: Ian Jiang <ianjiang.ict@gmail.com>, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de
Subject: Re: [PATCH v2] riscv: Add helper to make NaN-boxing for FP register
Date: Tue, 28 Jan 2020 10:32:29 -0800 [thread overview]
Message-ID: <b14a65dd-b565-77ca-d479-f88e53ca0721@linaro.org> (raw)
In-Reply-To: <20200128003707.17028-1-ianjiang.ict@gmail.com>
On 1/27/20 4:37 PM, Ian Jiang wrote:
> The function that makes NaN-boxing when a 32-bit value is assigned
> to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
> Then it is applied in translating of the FLW instruction.
>
> Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
> ---
> target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-01-28 19:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 0:37 [PATCH v2] riscv: Add helper to make NaN-boxing for FP register Ian Jiang
2020-01-28 0:41 ` Alistair Francis
2020-01-28 18:32 ` Richard Henderson [this message]
2020-06-09 10:07 ` Chih-Min Chao
2020-06-09 23:16 ` Alistair Francis
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