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Tue, 30 Sep 2025 11:08:40 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27eea801b49sm138585805ad.23.2025.09.30.11.08.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Sep 2025 11:08:39 -0700 (PDT) Message-ID: Date: Tue, 30 Sep 2025 11:08:38 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 00/34] single-binary: Make riscv cpu.h target independent Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com References: <20250924072124.6493-1-anjo@rev.ng> <427722cf-c91c-4c2f-b5a0-8d127c3dddea@linaro.org> <6c899106-ca29-4165-8769-2376f5eb5b07@linaro.org> From: Pierrick Bouvier In-Reply-To: <6c899106-ca29-4165-8769-2376f5eb5b07@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/29/25 7:03 PM, Philippe Mathieu-Daudé wrote: > On 30/9/25 00:44, Pierrick Bouvier wrote: > >> On 9/24/25 12:20 AM, Anton Johansson wrote: > >>> Quick question to correct my understanding. AFAICT riscv64-softmmu is a >>> superset of riscv32-softmmu which handles 32-, 64, and 128-bit ISAs, so >>> concerning single-binary do we for the time being only need to support >>> riscv64-softmmu? > > You are correct in that they are all part of the same architecture, > the register bits accessed being a mode of a CPU. > > IMO The "superset" view comes from QEMU historical development, and > I suspect a generic riscv-softmmu could be sufficient here. > > >> Overall, most of the changes you do are correct, widening types, and >> combining low/high part in single 64 bits integer. For this last part, >> I'll let Riscv maintainers decide if they agree with the approach. >> >> However, the main issue is that changing size impacts migration >> (VMSTATE_UINT.*), which would suddenly create a breaking change when >> importing 32 bits machines. >> >> We have two ways to deal with it: >> 1. call it a day and make a breaking change. >> On Arm side, we were lucky to not have cpu structure defined with any >> target type, so the problem was not found yet. But we observed that >> other architectures would need a solution. >> If Riscv maintainers are ok for a breaking change, this is the easiest/ >> fastest solution. >> >> 2. introduce a backward compatibility change, to selectively import size >> if we import from a past QEMU version. In this case, we would keep the >> VMSTATE_UINTTL but adapt it to do the right thing when restoring, either >> writing 32 or 64 bits. >> I didn't dive deep enough in migration restore code to see if it's >> easily doable, or not. > IMHO we should really avoid (2). The only problematic architectures (wrt > migration) are PPC and X86. Indeed, it looks like a nightmare and an excellent maintenance burden. I saw after sending my email that Alistair was open to a breaking change, so that's a good news!