From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
Date: Thu, 11 Nov 2021 12:46:54 +0100 [thread overview]
Message-ID: <b1d8f47a-a6fc-3d49-89dd-2ec0af867999@linaro.org> (raw)
In-Reply-To: <20211111055800.42672-20-zhiwei_liu@c-sky.com>
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> int maxsz = s->vlen >> 3;
> TCGv_i64 t1;
> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
A reminder that this is zero-extend for v0.7.1 and sign-extend for v1.0.0.
> @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> }
>
> t1 = tcg_temp_new_i64();
> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
> + tcg_gen_extu_tl_i64(t1, src1);
Likewise.
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> done:
> @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
> (a->rd != a->rs2));
> }
>
> +/* OPIVXU without GVEC IR */
> +#define GEN_OPIVXU_TRANS(NAME, CHECK) \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> +{ \
> + if (CHECK(s, a)) { \
> + static gen_helper_opivx * const fns[4] = { \
> + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
> + }; \
> + \
> + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
> + fns[s->sew], s, EXT_ZERO); \
> + } \
> + return false; \
> +}
> +
> GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
> -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
> +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
> GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
>
> GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
> -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
> +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
> GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
Likewise.
So if this patch set goes in after rvv 1.0, this whole patch may be dropped.
r~
next prev parent reply other threads:[~2021-11-11 11:47 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 5:57 [PATCH v3 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 11:19 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 11:21 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 11:26 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 11:28 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 11:29 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 11:31 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 11:35 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 11:38 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 11:46 ` Richard Henderson [this message]
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 5:58 ` [PATCH v3 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 11:49 ` Richard Henderson
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 18:20 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b1d8f47a-a6fc-3d49-89dd-2ec0af867999@linaro.org \
--to=richard.henderson@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@c-sky.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).