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[111.249.81.178]) by smtp.gmail.com with ESMTPSA id f1-20020a170902860100b001c61901ed2esm6001426plo.219.2023.11.06.07.21.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Nov 2023 07:21:57 -0800 (PST) Date: Mon, 6 Nov 2023 23:21:48 +0800 From: Jerry ZJ To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Daniel Henrique Barboza Message-ID: In-Reply-To: References: <20231106111440.59995-1-jerry.zhangjian@sifive.com> Subject: Re: [PATCH] target/riscv: don't enable Zfa by default X-Readdle-Message-ID: b1df8107-d0f1-4827-94bd-3f8c7cd3ea57@Spark MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="65490491_7ee28cfa_135e7" Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=jerry.zhangjian@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --65490491_7ee28cfa_135e7 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline We do have some cases that failed. SiFive e-series cores (https://static.dev.sifive.com/SiFive-E21-Manual-v1p0.pdf) do not have F extension (For example: rv32imc_zicsr_zifencei_zba_zbb). When we use the corresponding extension options to configure QEMU, i.e., rv32, i=true, m=true, a=true, c=true, Zicsr=true, Zifencei=true, zba=true, zbb=true, the QEMU will have the following error. Zfa extension requires F extension IMHO, we should not enable Zfa extension by default, especially when Zfa requires F to be enabled implicitly. Best Regards, Jerry ZJ SiFive Inc. Taiwan On Nov 6, 2023 at 22:55 +0800, Daniel Henrique Barboza , wrote: > > > On 11/6/23 08:14, Jerry Zhang Jian wrote: > > - Zfa requires F, we should not assume all CPUs have F extension > > support. > > We do not have a case where this happen, do we? The default CPUs have F > enabled (see misa_ext_cfgs[] in target/riscv/tcg/tcg-cpu.c), so zfa being > enable isn't a problem for them. Vendor CPUs might not have F enabled, but > they don't use the default values for extensions, so they're not affected. > Having zfa enabled by default does not hurt the default CPU setups we have. > > I am not a fan of these defaults for rv64 and so on, but once we set them to > 'true' people can complain if we set them to 'false' because it might break > existing configs in the wild. We need a strong case (i.e. a bug) to do so. > > > Thanks, > > Daniel > > > > > > Signed-off-by: Jerry Zhang Jian > > --- > > target/riscv/cpu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index ac4a6c7eec..c9f11509c8 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -1247,7 +1247,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > > MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), > > MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true), > > - MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true), > > + MULTI_EXT_CFG_BOOL("zfa", ext_zfa, false), > > MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false), > > MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false), > > MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), --65490491_7ee28cfa_135e7 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
We do have some cases that failed. Si=46ive e-serie= s cores (https://static.dev.sifive.com/Si=46ive= -E21-Manual-v1p0.pdf) do not have =46 extension (=46or example: rv32i= mc=5Fzicsr=5Fzifencei=5Fzba=5Fzbb). When we use the corresponding extensi= on options to configure QEMU, i.e., rv32, i=3Dtrue, m=3Dtrue, a=3Dtrue, c= =3Dtrue, Zicsr=3Dtrue, Zifencei=3Dtrue, zba=3Dtrue, zbb=3Dtrue, the QEMU = will have the following error.
Zfa extension requires =46= extension

IMHO, we should not enable Zfa extension by default, especially when Zfa = requires =46 to be enabled implicitly.

Best Regards,
Jerry ZJ
Si=46ive Inc. Taiwan
On Nov 6, 2023 at 22:55 +0800, Dani= el Henrique Barboza <dbarboza=40ventanamicro.com>, wrote:


On 11/6/23 08:14, Jerry Zhang Jian wrote:
- Zfa requires =46, we should not assume al= l CPUs have =46 extension
support.

We do not have a case where this happen, do we=3F The default CPUs have =46=
enabled (see misa=5Fext=5Fcfgs=5B=5D in target/riscv/tcg/tcg-cpu.c), so z= fa being
enable isn't a problem for them. Vendor CPUs might not have =46 enabled, = but
they don't use the default values for extensions, so they're not affected= .
Having zfa enabled by default does not hurt the default CPU setups we hav= e.

I am not a fan of these defaults for rv64 and so on, but once we set them= to
'true' people can complain if we set them to 'false' because it might bre= ak
existing configs in the wild. We need a strong case (i.e. a bug) to do so= .


Thanks,

Daniel



Signed-off-by: Jerry Zhang Jian <jerry.zhangjian=40sifive.com>
---
target/riscv/cpu.c =7C 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac4a6c7eec..c9f11509c8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
=40=40 -1247,7 +1247,7 =40=40 const RISCVCPUMultiExtConfig riscv=5Fcpu=5F= extensions=5B=5D =3D =7B
MULTI=5FEXT=5FC=46G=5FBOOL(=22zihintntl=22, ext=5Fzihintntl, true),
= MULTI=5FEXT=5FC=46G=5FBOOL(=22zihintpause=22, ext=5Fzihintpause, true), MULTI=5FEXT=5FC=46G=5FBOOL(=22zawrs=22, ext=5Fzawrs, true),
- MULTI=5FEXT=5FC=46G=5FBOOL(=22zfa=22, ext=5Fzfa, true),
+ MULTI=5FEXT=5FC=46G=5FBOOL(=22zfa=22, ext=5Fzfa, false),
MULTI=5FEXT=5FC=46G=5FBOOL(=22zfh=22, ext=5Fzfh, false),
MULTI=5FEXT=5FC=46G=5FBOOL(=22zfhmin=22, ext=5Fzfhmin, false),
MULTI=5FEXT=5FC=46G=5FBOOL(=22zve32f=22, ext=5Fzve32f, false),
--65490491_7ee28cfa_135e7--