From: Richard Henderson <richard.henderson@linaro.org>
To: "Cédric Le Goater" <clg@kaod.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>
Subject: Re: [PATCH 1/2] target/arm: Disable VFPv4-D32 when NEON is not available
Date: Wed, 28 Sep 2022 10:21:24 -0700 [thread overview]
Message-ID: <b2048335-768b-b3b7-d51e-c96ae8d0763b@linaro.org> (raw)
In-Reply-To: <20220928164719.655586-2-clg@kaod.org>
On 9/28/22 09:47, Cédric Le Goater wrote:
> As the Cortex A7 MPCore Technical reference says :
>
> "When FPU option is selected without NEON, the FPU is VFPv4-D16 and
> uses 16 double-precision registers. When the FPU is implemented with
> NEON, the FPU is VFPv4-D32 and uses 32 double-precision registers.
> This register bank is shared with NEON."
>
> Modify the mvfr0 register value of the cortex A7 to advertise only 16
> registers when NEON is not available, and not 32 registers.
Looks like A5 has the same language, while A15 says that NEON cannot be enabled without
VFP (which is the same as all aarch64 cores). I guess this is a decent compromise.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-09-28 17:25 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 16:47 [PATCH 0/2] ast2600: Disable NEON and VFPv4-D32 Cédric Le Goater
2022-09-28 16:47 ` [PATCH 1/2] target/arm: Disable VFPv4-D32 when NEON is not available Cédric Le Goater
2022-09-28 17:21 ` Richard Henderson [this message]
2022-09-28 23:00 ` Joel Stanley
2022-09-29 7:20 ` Cédric Le Goater
2022-09-29 11:48 ` Peter Maydell
2022-09-29 11:44 ` Peter Maydell
2022-09-29 15:22 ` Richard Henderson
2022-09-29 15:29 ` Peter Maydell
2022-09-30 14:59 ` Cédric Le Goater
2022-09-30 15:10 ` Peter Maydell
2022-09-28 16:47 ` [PATCH 2/2] ast2600: Drop NEON from the CPU features Cédric Le Goater
2022-09-29 2:09 ` Joel Stanley
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