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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id q26-20020aa7843a000000b00535da15a252sm4216495pfn.165.2022.09.28.10.21.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 10:21:26 -0700 (PDT) Message-ID: Date: Wed, 28 Sep 2022 10:21:24 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/2] target/arm: Disable VFPv4-D32 when NEON is not available Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Joel Stanley , Andrew Jeffery References: <20220928164719.655586-1-clg@kaod.org> <20220928164719.655586-2-clg@kaod.org> From: Richard Henderson In-Reply-To: <20220928164719.655586-2-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/28/22 09:47, Cédric Le Goater wrote: > As the Cortex A7 MPCore Technical reference says : > > "When FPU option is selected without NEON, the FPU is VFPv4-D16 and > uses 16 double-precision registers. When the FPU is implemented with > NEON, the FPU is VFPv4-D32 and uses 32 double-precision registers. > This register bank is shared with NEON." > > Modify the mvfr0 register value of the cortex A7 to advertise only 16 > registers when NEON is not available, and not 32 registers. Looks like A5 has the same language, while A15 says that NEON cannot be enabled without VFP (which is the same as all aarch64 cores). I guess this is a decent compromise. Reviewed-by: Richard Henderson r~