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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id az14-20020a056808164e00b003946655b791sm1461063oib.34.2023.05.15.03.12.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 May 2023 03:12:02 -0700 (PDT) Message-ID: Date: Mon, 15 May 2023 07:11:59 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3] target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs To: Richard Purdie , qemu-devel@nongnu.org Cc: =?UTF-8?Q?V=c3=adctor_Colombo?= , Matheus Ferst , Richard Henderson , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20230510111913.1718734-1-richard.purdie@linuxfoundation.org> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20230510111913.1718734-1-richard.purdie@linuxfoundation.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.93, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 5/10/23 08:19, Richard Purdie wrote: > The following commits changed the code such that the fallback to MFSS for MFFSCRN, > MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal instruction: > > bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree > 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree > 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree > > The hardware will handle them as a MFFS instruction as the code did previously. > This means applications that were segfaulting under qemu when encountering these > instructions which is used in glibc libm functions for example. > > The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing. > > This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs > as the hardware decoder would, fixing the segfaulting libm code. It doesn't have > the fallback for 3.0 onwards to match hardware behaviour. > > Signed-off-by: Richard Purdie > --- > target/ppc/insn32.decode | 20 +++++++++++++------- > target/ppc/translate/fp-impl.c.inc | 22 ++++++++++++++++------ > 2 files changed, 29 insertions(+), 13 deletions(-) > > v3 - drop fallback to MFFS for 3.0 ISA to match hardware > v2 - switch to use decodetree pattern groups per feedback > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index f8f589e9fd..4fcf3af8d0 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -390,13 +390,19 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi > > ### Move To/From FPSCR > > -MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc > -MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t > -MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb > -MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb > -MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 > -MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 > -MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t > +{ > + # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored > + MFFS_ISA207 111111 ..... ----- ----- 1001000111 . @X_t_rc > + [ > + MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc > + MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t > + MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb > + MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb > + MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 > + MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 > + MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t > + ] > +} > > ### Decimal Floating-Point Arithmetic Instructions > > diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc > index 57d8437851..874774eade 100644 > --- a/target/ppc/translate/fp-impl.c.inc > +++ b/target/ppc/translate/fp-impl.c.inc > @@ -568,6 +568,22 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask, > gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); > } > > +static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a) > +{ > + if (!(ctx->insns_flags2 & PPC2_ISA300)) { > + /* > + * Before Power ISA v3.0, MFFS bits 11~15 were reserved, any instruction > + * with OPCD=63 and XO=583 should be decoded as MFFS. > + */ > + return trans_MFFS(ctx, a); > + } > + /* > + * For Power ISA v3.0+, return false and let the pattern group > + * select the correct instruction. > + */ > + return false; > +} > + > static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) > { > REQUIRE_FPU(ctx); > @@ -584,7 +600,6 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) > { > TCGv_i64 fpscr; > > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > gen_reset_fpstatus(); > @@ -597,7 +612,6 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) > { > TCGv_i64 t1, fpscr; > > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > t1 = tcg_temp_new_i64(); > @@ -614,7 +628,6 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a) > { > TCGv_i64 t1, fpscr; > > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > t1 = tcg_temp_new_i64(); > @@ -631,7 +644,6 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) > { > TCGv_i64 t1, fpscr; > > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > t1 = tcg_temp_new_i64(); > @@ -647,7 +659,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) > { > TCGv_i64 t1, fpscr; > > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > t1 = tcg_temp_new_i64(); > @@ -661,7 +672,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) > > static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) > { > - REQUIRE_INSNS_FLAGS2(ctx, ISA300); > REQUIRE_FPU(ctx); > > gen_reset_fpstatus();