From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 4/5] target/arm: Add ID register values for Cortex-M0
Date: Fri, 11 Sep 2020 12:31:09 -0700 [thread overview]
Message-ID: <b22fcb17-f38b-e699-0c33-a3055d2427b7@linaro.org> (raw)
In-Reply-To: <20200910173855.4068-5-peter.maydell@linaro.org>
On 9/10/20 10:38 AM, Peter Maydell wrote:
> Give the Cortex-M0 ID register values corresponding to its
> implemented behaviour. These will not be guest-visible but will be
> used to govern the behaviour of QEMU's emulation. We use the same
> values that the Cortex-M3 does.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-09-11 19:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 17:38 [PATCH 0/5] handle M-profile in fp16_arith isar_feature test Peter Maydell
2020-09-10 17:38 ` [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Peter Maydell
2020-09-11 19:27 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 2/5] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters Peter Maydell
2020-09-11 19:28 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs Peter Maydell
2020-09-11 19:30 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 4/5] target/arm: Add ID register values for Cortex-M0 Peter Maydell
2020-09-11 19:31 ` Richard Henderson [this message]
2020-09-10 17:38 ` [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile Peter Maydell
2020-09-11 19:32 ` Richard Henderson
2020-09-11 19:40 ` [PATCH 0/5] handle M-profile in fp16_arith isar_feature test Richard Henderson
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