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Mon, 09 May 2022 05:56:27 -0700 (PDT) Message-ID: Date: Mon, 9 May 2022 14:24:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 3/7] target/mips: Fix emulation of nanoMips BPOSGE32C instruction Content-Language: en-US To: Stefan Pejic , qemu-devel@nongnu.org Cc: ot_stefan.pejic@mediatek.com, ot_dragan.mladjenovic@mediatek.com, Dragan Mladjenovic References: <20220504110403.613168-1-stefan.pejic@syrmia.com> <20220504110403.613168-4-stefan.pejic@syrmia.com> In-Reply-To: <20220504110403.613168-4-stefan.pejic@syrmia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= via On 4/5/22 13:03, Stefan Pejic wrote: > From: Dragan Mladjenovic > > There are currently two problems related to the emulation of the > instruction BPOSGE32C. > > The nanoMips instruction BPOSGE32C belongs to DSP R3 instructions > (actually, as of now, it is the only instruction of DSP R3). The > presence of DSP R3 instructions in QEMU is indicated by the flag > MIPS_HFLAG_DSP_R3 (0x20000000). This flag is currently being properly > set in CPUMIPSState's hflags (for example, for I7200 nanoMips CPU). > However, it is not propagated to DisasContext's hflags, since the flag > MIPS_HFLAG_DSP_R3 is not set in MIPS_HFLAG_TMASK (while similar flags > MIPS_HFLAG_DSP_R2 and MIPS_HFLAG_DSP are set in this mask, and there > is no problem in functioning check_dsp_r2(), check_dsp()). This means > the function check_dsp_r3() currently does not work properly, and the > emulation of BPOSGE32C can not work properly as well. > > Change MIPS_HFLAG_TMASK from 0x1F5807FF to 0x3F5807FF (logical OR > with 0x20000000) to fix this. > > Additionally, check_cp1_enabled() is currently incorrectly called > while emulating BPOSGE32C. BPOSGE32C is in the same pool (P.BR1) as > FPU branch instruction BC1EQZC and BC1NEZC, but it not a part of FPU > (CP1) instructions, and check_cp1_enabled() should not be involved > while emulating BPOSGE32C. > > Rearrange invocations of check_cp1_enabled() within P.BR1 pool > handling to affect only BC1EQZC and BC1NEZC emulation, and not > BPOSGE32C emulation. > > Signed-off-by: Dragan Mladjenovic > Signed-off-by: Stefan Pejic > --- > target/mips/cpu.h | 2 +- > target/mips/tcg/nanomips_translate.c.inc | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé