[PATCH 0/7] Undeprecate nanoMIPS and fix multiple bugs

[PATCH 0/7] Undeprecate nanoMIPS and fix multiple bugs

[Stefan Pejic]

This series of patches aims to undeprecate nanoMIPS architecture and fix
several issues that were found in recent testings.

Dragan Mladjenovic (4):
  target/mips: Fix emulation of nanoMips EXTRV_S.H instruction
  target/mips: Fix emulation of nanoMips BPOSGE32C instruction
  target/mips: Fix emulation of nanoMips BNEC[32] instruction
  target/mips: Fix handling of unaligned memory access for nanoMips ISA

Stefan Pejic (3):
  target/mips: Fix emulation of nanoMips MTHLIP instruction
  target/mips: Add missing default cases for some nanoMips pools
  target/mips: Undeprecate nanoMips ISA support in QEMU

 MAINTAINERS                              |  3 ++-
 docs/about/deprecated.rst                | 26 -------------------
 target/mips/cpu.h                        |  2 +-
 target/mips/tcg/nanomips_translate.c.inc | 33 +++++++++++++++++++++---
 target/mips/tcg/translate.c              |  5 ++--
 5 files changed, 35 insertions(+), 34 deletions(-)

-- 
2.25.1

[PATCH 1/7] target/mips: Fix emulation of nanoMips MTHLIP instruction

[Stefan Pejic]

The field ac in nanoMips instruction MTHLIP rs, ac is specified in
nanoMips documentation as opcode[15..14] (2 bits). However, in the
current QEMU code, the corresponding argument passed to the helper
gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right
shift the value of this argument by three bits to fix this.

Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/tcg/nanomips_translate.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 916cece4d2..58ae35a156 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1597,7 +1597,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
         check_dsp(ctx);
         switch (extract32(ctx->opcode, 12, 2)) {
         case NM_MTHLIP:
-            tcg_gen_movi_tl(t0, v2);
+            tcg_gen_movi_tl(t0, v2 >> 3);
             gen_helper_mthlip(t0, v0_t, cpu_env);
             break;
         case NM_SHILOV:
-- 
2.25.1

Re: [PATCH 1/7] target/mips: Fix emulation of nanoMips MTHLIP instruction

[Philippe Mathieu-Daudé via]

Hi Stefan,

On 4/5/22 13:03, Stefan Pejic wrote:
> The field ac in nanoMips instruction MTHLIP rs, ac is specified in
> nanoMips documentation as opcode[15..14] (2 bits). However, in the
> current QEMU code, the corresponding argument passed to the helper
> gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right
> shift the value of this argument by three bits to fix this.

Indeed. This applies to all the class, so
gen_pool32axf_1_nanomips_insn() could directly take (shifted) 'ac'
argument instead of v2.

Anyhow:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/nanomips_translate.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
> index 916cece4d2..58ae35a156 100644
> --- a/target/mips/tcg/nanomips_translate.c.inc
> +++ b/target/mips/tcg/nanomips_translate.c.inc
> @@ -1597,7 +1597,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
>           check_dsp(ctx);
>           switch (extract32(ctx->opcode, 12, 2)) {
>           case NM_MTHLIP:
> -            tcg_gen_movi_tl(t0, v2);
> +            tcg_gen_movi_tl(t0, v2 >> 3);
>               gen_helper_mthlip(t0, v0_t, cpu_env);
>               break;
>           case NM_SHILOV:

[PATCH 2/7] target/mips: Fix emulation of nanoMips EXTRV_S.H instruction

[Stefan Pejic]

From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
nanoMips documentation as opcode[20..16]. It is, however, erroneously
considered as opcode[25..21] in the current QEMU implementation. In
function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds
to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and
v0_t is by mistake passed to the helper gen_helper_extr_s_h().

Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h()
to fix this.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/tcg/nanomips_translate.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 58ae35a156..9ee4df2135 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
         case NM_EXTRV_S_H:
             check_dsp(ctx);
             tcg_gen_movi_tl(t0, rd >> 3);
-            gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
+            gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
             gen_store_gpr(t0, ret);
             break;
         }
-- 
2.25.1

Re: [PATCH 2/7] target/mips: Fix emulation of nanoMips EXTRV_S.H instruction

[Philippe Mathieu-Daudé via]

On 4/5/22 13:03, Stefan Pejic wrote:
> From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
> nanoMips documentation as opcode[20..16]. It is, however, erroneously
> considered as opcode[25..21] in the current QEMU implementation. In
> function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds
> to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and
> v0_t is by mistake passed to the helper gen_helper_extr_s_h().
> 
> Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h()
> to fix this.
> 

Fixes: 8b3698b294 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/nanomips_translate.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
> index 58ae35a156..9ee4df2135 100644
> --- a/target/mips/tcg/nanomips_translate.c.inc
> +++ b/target/mips/tcg/nanomips_translate.c.inc
> @@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
>           case NM_EXTRV_S_H:
>               check_dsp(ctx);
>               tcg_gen_movi_tl(t0, rd >> 3);
> -            gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
> +            gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
>               gen_store_gpr(t0, ret);
>               break;
>           }

[PATCH 3/7] target/mips: Fix emulation of nanoMips BPOSGE32C instruction

[Stefan Pejic]

From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

There are currently two problems related to the emulation of the
instruction BPOSGE32C.

The nanoMips instruction BPOSGE32C belongs to DSP R3 instructions
(actually, as of now, it is the only instruction of DSP R3). The
presence of DSP R3 instructions in QEMU is indicated by the flag
MIPS_HFLAG_DSP_R3 (0x20000000). This flag is currently being properly
set in CPUMIPSState's hflags (for example, for I7200 nanoMips CPU).
However, it is not propagated to DisasContext's hflags, since the flag
MIPS_HFLAG_DSP_R3 is not set in MIPS_HFLAG_TMASK (while similar flags
MIPS_HFLAG_DSP_R2 and MIPS_HFLAG_DSP are set in this mask, and there
is no problem in functioning check_dsp_r2(), check_dsp()). This means
the function check_dsp_r3() currently does not work properly, and the
emulation of BPOSGE32C can not work properly as well.

Change MIPS_HFLAG_TMASK from 0x1F5807FF to 0x3F5807FF (logical OR
with 0x20000000) to fix this.

Additionally, check_cp1_enabled() is currently incorrectly called
while emulating BPOSGE32C. BPOSGE32C is in the same pool (P.BR1) as
FPU branch instruction BC1EQZC and BC1NEZC, but it not a part of FPU
(CP1) instructions, and check_cp1_enabled() should not be involved
while emulating BPOSGE32C.

Rearrange invocations of check_cp1_enabled() within P.BR1 pool
handling to affect only BC1EQZC and BC1NEZC emulation, and not
BPOSGE32C emulation.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/cpu.h                        | 2 +-
 target/mips/tcg/nanomips_translate.c.inc | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5335ac10a3..04812e84d5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1076,7 +1076,7 @@ typedef struct CPUArchState {
 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
     uint32_t hflags;    /* CPU State */
     /* TMASK defines different execution modes */
-#define MIPS_HFLAG_TMASK  0x1F5807FF
+#define MIPS_HFLAG_TMASK  0x3F5807FF
 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
     /*
      * The KSU flags must be the lowest bits in hflags. The flag order
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 9ee4df2135..941cfaa6bb 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4478,12 +4478,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             case NM_P_BR3A:
                 s = sextract32(ctx->opcode, 0, 1) << 14 |
                     extract32(ctx->opcode, 1, 13) << 1;
-                check_cp1_enabled(ctx);
                 switch (extract32(ctx->opcode, 16, 5)) {
                 case NM_BC1EQZC:
+                    check_cp1_enabled(ctx);
                     gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
                     break;
                 case NM_BC1NEZC:
+                    check_cp1_enabled(ctx);
                     gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
                     break;
                 case NM_BPOSGE32C:
-- 
2.25.1

Re: [PATCH 3/7] target/mips: Fix emulation of nanoMips BPOSGE32C instruction

[Philippe Mathieu-Daudé via]

On 4/5/22 13:03, Stefan Pejic wrote:
> From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> There are currently two problems related to the emulation of the
> instruction BPOSGE32C.
> 
> The nanoMips instruction BPOSGE32C belongs to DSP R3 instructions
> (actually, as of now, it is the only instruction of DSP R3). The
> presence of DSP R3 instructions in QEMU is indicated by the flag
> MIPS_HFLAG_DSP_R3 (0x20000000). This flag is currently being properly
> set in CPUMIPSState's hflags (for example, for I7200 nanoMips CPU).
> However, it is not propagated to DisasContext's hflags, since the flag
> MIPS_HFLAG_DSP_R3 is not set in MIPS_HFLAG_TMASK (while similar flags
> MIPS_HFLAG_DSP_R2 and MIPS_HFLAG_DSP are set in this mask, and there
> is no problem in functioning check_dsp_r2(), check_dsp()). This means
> the function check_dsp_r3() currently does not work properly, and the
> emulation of BPOSGE32C can not work properly as well.
> 
> Change MIPS_HFLAG_TMASK from 0x1F5807FF to 0x3F5807FF (logical OR
> with 0x20000000) to fix this.
> 
> Additionally, check_cp1_enabled() is currently incorrectly called
> while emulating BPOSGE32C. BPOSGE32C is in the same pool (P.BR1) as
> FPU branch instruction BC1EQZC and BC1NEZC, but it not a part of FPU
> (CP1) instructions, and check_cp1_enabled() should not be involved
> while emulating BPOSGE32C.
> 
> Rearrange invocations of check_cp1_enabled() within P.BR1 pool
> handling to affect only BC1EQZC and BC1NEZC emulation, and not
> BPOSGE32C emulation.
> 
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/cpu.h                        | 2 +-
>   target/mips/tcg/nanomips_translate.c.inc | 3 ++-
>   2 files changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

[PATCH 4/7] target/mips: Fix emulation of nanoMips BNEC[32] instruction

[Stefan Pejic]

From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

If both rs and rt are the same register, the nanoMips instruction
BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
there is no delay slot). This commit provides such behavior. Without
this commit, this scenario results in an incorrect behavior.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/tcg/nanomips_translate.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 941cfaa6bb..1ee5c8c8d4 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4528,7 +4528,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             switch (extract32(ctx->opcode, 14, 2)) {
             case NM_BNEC:
                 check_nms(ctx);
-                gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
+                if (rs == rt) {
+                    /* NOP */
+                    ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+                } else {
+                    gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
+                }
                 break;
             case NM_BLTC:
                 if (rs != 0 && rt != 0 && rs == rt) {
-- 
2.25.1

Re: [PATCH 4/7] target/mips: Fix emulation of nanoMips BNEC[32] instruction

[Philippe Mathieu-Daudé via]

On 4/5/22 13:04, Stefan Pejic wrote:
> From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> If both rs and rt are the same register, the nanoMips instruction
> BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
> there is no delay slot). This commit provides such behavior. Without
> this commit, this scenario results in an incorrect behavior.
> 
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/nanomips_translate.c.inc | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

[PATCH 5/7] target/mips: Fix handling of unaligned memory access for nanoMips ISA

[Stefan Pejic]

From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

nanoMips ISA does not support unaligned memory access. Adjust
DisasContext's default_tcg_memop_mask to reflect this.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/tcg/translate.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..5f460fb687 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16023,8 +16023,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
         ctx->mem_idx = hflags_mmu_index(ctx->hflags);
 #endif
-    ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
-                                  INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
+    ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
+                                  (ctx->insn_flags & (ISA_MIPS_R6 |
+                                  INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
 
     /*
      * Execute a branch and its delay slot as a single instruction.
-- 
2.25.1

Re: [PATCH 5/7] target/mips: Fix handling of unaligned memory access for nanoMips ISA

[Philippe Mathieu-Daudé via]

On 4/5/22 13:04, Stefan Pejic wrote:
> From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> nanoMips ISA does not support unaligned memory access. Adjust
> DisasContext's default_tcg_memop_mask to reflect this.
> 
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/translate.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

[PATCH 6/7] target/mips: Add missing default cases for some nanoMips pools

[Stefan Pejic]

Switch statements for the code segments that handle nanoMips
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.

Fix this by adding default cases for these switch statements that
trigger reserved instruction exception.

Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 target/mips/tcg/nanomips_translate.c.inc | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 1ee5c8c8d4..c0ba2bf1b1 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2707,6 +2707,9 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
         case NM_SDC1XS:
             tcg_gen_shli_tl(t0, t0, 3);
             break;
+        default:
+            gen_reserved_instruction(ctx);
+            goto out;
         }
     }
     gen_op_addr_add(ctx, t0, t0, t1);
@@ -2797,6 +2800,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
         break;
     }
 
+out:
     tcg_temp_free(t0);
     tcg_temp_free(t1);
 }
@@ -3944,6 +3948,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     gen_shift_imm(ctx, OPC_ROTR, rt, rs,
                                   extract32(ctx->opcode, 0, 5));
                     break;
+                default:
+                    gen_reserved_instruction(ctx);
+                    break;
                 }
             }
             break;
@@ -4245,6 +4252,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         check_xnp(ctx);
                         gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
                         break;
+                    default:
+                        gen_reserved_instruction(ctx);
+                        break;
                     }
                     break;
                 case NM_P_SC:
@@ -4257,6 +4267,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
                                  false);
                         break;
+                    default:
+                        gen_reserved_instruction(ctx);
+                        break;
                     }
                     break;
                 case NM_CACHE:
@@ -4265,6 +4278,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         gen_cache_operation(ctx, rt, rs, s);
                     }
                     break;
+                default:
+                    gen_reserved_instruction(ctx);
+                    break;
                 }
                 break;
             case NM_P_LS_E0:
@@ -4371,6 +4387,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         break;
                     }
                     break;
+                default:
+                    gen_reserved_instruction(ctx);
+                    break;
                 }
                 break;
             case NM_P_LS_WM:
-- 
2.25.1

Re: [PATCH 6/7] target/mips: Add missing default cases for some nanoMips pools

[Philippe Mathieu-Daudé via]

On 4/5/22 13:04, Stefan Pejic wrote:
> Switch statements for the code segments that handle nanoMips
> instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
> do not have proper default case, resulting in not generating
> reserved instruction exception for certain illegal opcodes.
> 
> Fix this by adding default cases for these switch statements that
> trigger reserved instruction exception.
> 
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   target/mips/tcg/nanomips_translate.c.inc | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

[PATCH 7/7] target/mips: Undeprecate nanoMips ISA support in QEMU

[Stefan Pejic]

nanoMips ISA support in QEMU is actively used by MediaTek and is
planned to be maintained and potentially extended by MediaTek in
future.

Un-orphan nanoMips ISA support in QEMU by setting a mainainer from
MediaTek and remove deprecation notes from documentation as well.

Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
---
 MAINTAINERS               |  3 ++-
 docs/about/deprecated.rst | 26 --------------------------
 2 files changed, 2 insertions(+), 27 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 294c88ace9..f1e0dee8a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -240,7 +240,8 @@ F: docs/system/cpu-models-mips.rst.inc
 F: tests/tcg/mips/
 
 MIPS TCG CPUs (nanoMIPS ISA)
-S: Orphan
+M: Stefan Pejic <stefan.pejic@syrmia.com>
+S: Maintained
 F: disas/nanomips.*
 F: target/mips/tcg/*nanomips*
 
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 896e5a97ab..4b0868886f 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -276,13 +276,6 @@ System emulator CPUS
 ``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` CPU
 Models instead.
 
-MIPS ``I7200`` CPU Model (since 5.2)
-''''''''''''''''''''''''''''''''''''
-
-The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
-(the ISA has never been upstreamed to a compiler toolchain). Therefore
-this CPU is also deprecated.
-
 
 QEMU API (QAPI) events
 ----------------------
@@ -382,16 +375,6 @@ The above, converted to the current supported format::
 
   json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
 
-linux-user mode CPUs
---------------------
-
-MIPS ``I7200`` CPU (since 5.2)
-''''''''''''''''''''''''''''''
-
-The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
-(the ISA has never been upstreamed to a compiler toolchain). Therefore
-this CPU is also deprecated.
-
 Backwards compatibility
 -----------------------
 
@@ -421,15 +404,6 @@ versions, aliases will point to newer CPU model versions
 depending on the machine type, so management software must
 resolve CPU model aliases before starting a virtual machine.
 
-Guest Emulator ISAs
--------------------
-
-nanoMIPS ISA
-''''''''''''
-
-The ``nanoMIPS`` ISA has never been upstreamed to any compiler toolchain.
-As it is hard to generate binaries for it, declare it deprecated.
-
 Tools
 -----
 
-- 
2.25.1

Re: [PATCH 7/7] target/mips: Undeprecate nanoMips ISA support in QEMU

[Philippe Mathieu-Daudé via]

Hi Stefan,

On 4/5/22 13:04, Stefan Pejic wrote:
> nanoMips ISA support in QEMU is actively used by MediaTek and is
> planned to be maintained and potentially extended by MediaTek in
> future.
> 
> Un-orphan nanoMips ISA support in QEMU by setting a mainainer from
> MediaTek and remove deprecation notes from documentation as well.
> 
> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
> ---
>   MAINTAINERS               |  3 ++-
>   docs/about/deprecated.rst | 26 --------------------------
>   2 files changed, 2 insertions(+), 27 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 294c88ace9..f1e0dee8a2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -240,7 +240,8 @@ F: docs/system/cpu-models-mips.rst.inc
>   F: tests/tcg/mips/
>   
>   MIPS TCG CPUs (nanoMIPS ISA)
> -S: Orphan
> +M: Stefan Pejic <stefan.pejic@syrmia.com>
> +S: Maintained
>   F: disas/nanomips.*
>   F: target/mips/tcg/*nanomips*
>   
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index 896e5a97ab..4b0868886f 100644
> --- a/docs/about/deprecated.rst
> +++ b/docs/about/deprecated.rst
> @@ -276,13 +276,6 @@ System emulator CPUS
>   ``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` CPU
>   Models instead.
>   
> -MIPS ``I7200`` CPU Model (since 5.2)
> -''''''''''''''''''''''''''''''''''''
> -
> -The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
> -(the ISA has never been upstreamed to a compiler toolchain). Therefore
> -this CPU is also deprecated.
> -
>   
>   QEMU API (QAPI) events
>   ----------------------
> @@ -382,16 +375,6 @@ The above, converted to the current supported format::
>   
>     json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
>   
> -linux-user mode CPUs
> ---------------------
> -
> -MIPS ``I7200`` CPU (since 5.2)
> -''''''''''''''''''''''''''''''
> -
> -The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
> -(the ISA has never been upstreamed to a compiler toolchain). Therefore
> -this CPU is also deprecated.

Thanks for contributing all these fixes! I'm glad to see this code used
and soon maintained again. Last time I tried to run a user-mode binary
it wasn't loading due to incomplete nanoMIPS ABI support. What kind of
tests are you running? Would it be possible to contributing them, to 
avoid code bitrotting?

Thanks,

Phil.

Re: [PATCH 7/7] target/mips: Undeprecate nanoMips ISA support in QEMU

[Philippe Mathieu-Daudé via]

Cc'ing Vince.

On 31/5/22 15:14, Philippe Mathieu-Daudé wrote:
> Hi Stefan,
> 
> On 4/5/22 13:04, Stefan Pejic wrote:
>> nanoMips ISA support in QEMU is actively used by MediaTek and is
>> planned to be maintained and potentially extended by MediaTek in
>> future.
>>
>> Un-orphan nanoMips ISA support in QEMU by setting a mainainer from
>> MediaTek and remove deprecation notes from documentation as well.
>>
>> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
>> ---
>>   MAINTAINERS               |  3 ++-
>>   docs/about/deprecated.rst | 26 --------------------------
>>   2 files changed, 2 insertions(+), 27 deletions(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 294c88ace9..f1e0dee8a2 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -240,7 +240,8 @@ F: docs/system/cpu-models-mips.rst.inc
>>   F: tests/tcg/mips/
>>   MIPS TCG CPUs (nanoMIPS ISA)
>> -S: Orphan
>> +M: Stefan Pejic <stefan.pejic@syrmia.com>
>> +S: Maintained
>>   F: disas/nanomips.*
>>   F: target/mips/tcg/*nanomips*
>> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
>> index 896e5a97ab..4b0868886f 100644
>> --- a/docs/about/deprecated.rst
>> +++ b/docs/about/deprecated.rst
>> @@ -276,13 +276,6 @@ System emulator CPUS
>>   ``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` 
>> CPU
>>   Models instead.
>> -MIPS ``I7200`` CPU Model (since 5.2)
>> -''''''''''''''''''''''''''''''''''''
>> -
>> -The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
>> -(the ISA has never been upstreamed to a compiler toolchain). Therefore
>> -this CPU is also deprecated.
>> -
>>   QEMU API (QAPI) events
>>   ----------------------
>> @@ -382,16 +375,6 @@ The above, converted to the current supported 
>> format::
>>     json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
>> -linux-user mode CPUs
>> ---------------------
>> -
>> -MIPS ``I7200`` CPU (since 5.2)
>> -''''''''''''''''''''''''''''''
>> -
>> -The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
>> -(the ISA has never been upstreamed to a compiler toolchain). Therefore
>> -this CPU is also deprecated.
> 
> Thanks for contributing all these fixes! I'm glad to see this code used
> and soon maintained again. Last time I tried to run a user-mode binary
> it wasn't loading due to incomplete nanoMIPS ABI support. What kind of
> tests are you running? Would it be possible to contributing them, to 
> avoid code bitrotting?
> 
> Thanks,
> 
> Phil.

Re: [PATCH 7/7] target/mips: Undeprecate nanoMips ISA support in QEMU

[Philippe Mathieu-Daudé via]

On 10/6/22 16:09, Philippe Mathieu-Daudé wrote:
> On 31/5/22 15:14, Philippe Mathieu-Daudé wrote:
>> On 4/5/22 13:04, Stefan Pejic wrote:
>>> nanoMips ISA support in QEMU is actively used by MediaTek and is
>>> planned to be maintained and potentially extended by MediaTek in
>>> future.
>>>
>>> Un-orphan nanoMips ISA support in QEMU by setting a mainainer from
>>> MediaTek and remove deprecation notes from documentation as well.
>>>
>>> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
>>> ---
>>>   MAINTAINERS               |  3 ++-
>>>   docs/about/deprecated.rst | 26 --------------------------
>>>   2 files changed, 2 insertions(+), 27 deletions(-)

>>> -The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
>>> -(the ISA has never been upstreamed to a compiler toolchain). Therefore
>>> -this CPU is also deprecated.
>>
>> Thanks for contributing all these fixes! I'm glad to see this code used
>> and soon maintained again. Last time I tried to run a user-mode binary
>> it wasn't loading due to incomplete nanoMIPS ABI support. What kind of
>> tests are you running? Would it be possible to contributing them, to 
>> avoid code bitrotting?

Any prebuilt binary I can use to test instructions coverage would do.

Re: [PATCH 0/7] Undeprecate nanoMIPS and fix multiple bugs

[Philippe Mathieu-Daudé via]

On 4/5/22 13:03, Stefan Pejic wrote:
> This series of patches aims to undeprecate nanoMIPS architecture and fix
> several issues that were found in recent testings.
> 
> Dragan Mladjenovic (4):
>    target/mips: Fix emulation of nanoMips EXTRV_S.H instruction
>    target/mips: Fix emulation of nanoMips BPOSGE32C instruction
>    target/mips: Fix emulation of nanoMips BNEC[32] instruction
>    target/mips: Fix handling of unaligned memory access for nanoMips ISA
> 
> Stefan Pejic (3):
>    target/mips: Fix emulation of nanoMips MTHLIP instruction
>    target/mips: Add missing default cases for some nanoMips pools
>    target/mips: Undeprecate nanoMips ISA support in QEMU

Thanks, queued to mips-next.