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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id gg7-20020a17090b0a0700b001d97f17f9b5sm9045435pjb.35.2022.05.07.04.35.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 07 May 2022 04:35:42 -0700 (PDT) Message-ID: Date: Sat, 7 May 2022 06:35:39 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH 0/5] gicv3: Use right number of prio bits for the CPU Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220506162129.2896966-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/6/22 11:21, Peter Maydell wrote: > This patchset fills in an odd inconsistency in our GICv3 emulation > that I noticed while I was doing the GICv4 work. At the moment we > allow the CPU to specify the number of bits of virtual priority > (via the ARMCPU::gic_vpribits field), but we always use 8 bits of > physical priority, even though to my knowledge no real Arm CPU > hardware has that many. > > This series makes the GICv3 emulation use a runtime-configurable > number of physical priority bits, and sets it to match the number > used by the various CPUs we implement (which is 5 for all the > Cortex-Axx CPUs we emulate). Because changing the number of > priority bits is a migration compatibility break, we use a compat > property to keep the number of priority bits at 8 for older > versions of the virt board. > > There is one TODO left in this series, which is that I don't know > the right value to use for the A64FX, so I've guessed that it > is 5, like all the Arm implementations. > > Patch 1 is an independent bugfix; patch 5 is cleanup. > > thanks > -- PMM > > Peter Maydell (5): > hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 > hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant > hw/intc/arm_gicv3: Support configurable number of physical priority > bits > hw/intc/arm_gicv3: Use correct number of priority bits for the CPU > hw/intc/arm_gicv3: Provide ich_num_aprs() > Reviewed-by: Richard Henderson r~