Re: [PATCH v1 1/1] hw/riscv: adding support for NeoRV32 RiscV MCU

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi Michael,

On 20/10/25 20:14, Michael Levit wrote:
> From: Michael <michael@videogpu.com>
> 
> 1) Initial support for Neorv32 soft-core MCU
> 2) IMEM, DMEM memory regions, bootloader ROM
> 3) Basic support for UART0 (no interrupts yet)
> 4) Basic support for SPI
> 5) Added SPI flash memory for loading firmware following  bootloader
> 6) Based on Neorv32 RTL implementation repo
>     https://github.com/stnolting/neorv32
>     commit id 7d0ef6b2
> 
> Signed-off-by: Michael Levit <michael@videogpu.com>
> ---
>   .gitignore                                  |   1 +
>   configs/devices/riscv32-softmmu/default.mak |   1 +
>   docs/system/riscv/neorv32.rst               | 110 +++++
>   hw/char/Kconfig                             |   3 +
>   hw/char/meson.build                         |   1 +
>   hw/char/neorv32_uart.c                      | 311 ++++++++++++
>   hw/misc/Kconfig                             |   2 +
>   hw/misc/meson.build                         |   1 +
>   hw/misc/neorv32_sysinfo.c                   | 183 +++++++
>   hw/misc/neorv32_sysinfo.h                   |  79 +++
>   hw/misc/neorv32_sysinfo_rtl.h               | 134 ++++++
>   hw/riscv/Kconfig                            |   8 +
>   hw/riscv/meson.build                        |   1 +
>   hw/riscv/neorv32.c                          | 219 +++++++++
>   hw/ssi/Kconfig                              |   4 +
>   hw/ssi/meson.build                          |   1 +
>   hw/ssi/neorv32_spi.c                        | 504 ++++++++++++++++++++
>   include/hw/char/neorv32_uart.h              |  68 +++
>   include/hw/riscv/neorv32.h                  |  60 +++
>   include/hw/ssi/neorv32_spi.h                |  70 +++
>   target/riscv/cpu-qom.h                      |   2 +
>   target/riscv/cpu.c                          |  18 +
>   target/riscv/cpu.h                          |   3 +
>   target/riscv/cpu_cfg.h                      |   1 +
>   target/riscv/cpu_cfg_fields.h.inc           |   1 +
>   target/riscv/cpu_vendorid.h                 |   2 +
>   target/riscv/meson.build                    |   1 +
>   target/riscv/neorv32_csr.c                  |  54 +++
>   28 files changed, 1843 insertions(+)

Thanks for your contribution! However I'm afraid this patch is too big
to be reviewed without missing something. I'd suggest splitting like
the 6 bullets you enumerated.

> diff --git a/.gitignore b/.gitignore
> index 61fa39967b..b53806de50 100644
> --- a/.gitignore
> +++ b/.gitignore
> @@ -9,6 +9,7 @@
>   .clang-format
>   .gdb_history
>   cscope.*
> +phases.hold

Not sure from where this file comes; maybe a shell typo?
Regards,

Phil.