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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427e1be5d6csm16630489f8f.0.2025.10.20.12.21.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Oct 2025 12:21:22 -0700 (PDT) Message-ID: Date: Mon, 20 Oct 2025 21:21:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/1] hw/riscv: adding support for NeoRV32 RiscV MCU Content-Language: en-US To: Michael Levit , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com References: <20251020181435.8242-1-michael@videogpu.com> <20251020181435.8242-2-michael@videogpu.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251020181435.8242-2-michael@videogpu.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Michael, On 20/10/25 20:14, Michael Levit wrote: > From: Michael > > 1) Initial support for Neorv32 soft-core MCU > 2) IMEM, DMEM memory regions, bootloader ROM > 3) Basic support for UART0 (no interrupts yet) > 4) Basic support for SPI > 5) Added SPI flash memory for loading firmware following bootloader > 6) Based on Neorv32 RTL implementation repo > https://github.com/stnolting/neorv32 > commit id 7d0ef6b2 > > Signed-off-by: Michael Levit > --- > .gitignore | 1 + > configs/devices/riscv32-softmmu/default.mak | 1 + > docs/system/riscv/neorv32.rst | 110 +++++ > hw/char/Kconfig | 3 + > hw/char/meson.build | 1 + > hw/char/neorv32_uart.c | 311 ++++++++++++ > hw/misc/Kconfig | 2 + > hw/misc/meson.build | 1 + > hw/misc/neorv32_sysinfo.c | 183 +++++++ > hw/misc/neorv32_sysinfo.h | 79 +++ > hw/misc/neorv32_sysinfo_rtl.h | 134 ++++++ > hw/riscv/Kconfig | 8 + > hw/riscv/meson.build | 1 + > hw/riscv/neorv32.c | 219 +++++++++ > hw/ssi/Kconfig | 4 + > hw/ssi/meson.build | 1 + > hw/ssi/neorv32_spi.c | 504 ++++++++++++++++++++ > include/hw/char/neorv32_uart.h | 68 +++ > include/hw/riscv/neorv32.h | 60 +++ > include/hw/ssi/neorv32_spi.h | 70 +++ > target/riscv/cpu-qom.h | 2 + > target/riscv/cpu.c | 18 + > target/riscv/cpu.h | 3 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/cpu_vendorid.h | 2 + > target/riscv/meson.build | 1 + > target/riscv/neorv32_csr.c | 54 +++ > 28 files changed, 1843 insertions(+) Thanks for your contribution! However I'm afraid this patch is too big to be reviewed without missing something. I'd suggest splitting like the 6 bullets you enumerated. > diff --git a/.gitignore b/.gitignore > index 61fa39967b..b53806de50 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -9,6 +9,7 @@ > .clang-format > .gdb_history > cscope.* > +phases.hold Not sure from where this file comes; maybe a shell typo? Regards, Phil.