From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KUd5b-0005tu-CA for qemu-devel@nongnu.org; Sun, 17 Aug 2008 03:54:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KUd5Y-0005tg-Id for qemu-devel@nongnu.org; Sun, 17 Aug 2008 03:54:14 -0400 Received: from [199.232.76.173] (port=46136 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KUd5Y-0005td-Ck for qemu-devel@nongnu.org; Sun, 17 Aug 2008 03:54:12 -0400 Received: from rv-out-0708.google.com ([209.85.198.249]:65321) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KUd5X-0005tc-Lp for qemu-devel@nongnu.org; Sun, 17 Aug 2008 03:54:12 -0400 Received: by rv-out-0708.google.com with SMTP id f25so1405019rvb.22 for ; Sun, 17 Aug 2008 00:54:10 -0700 (PDT) Message-ID: Date: Sun, 17 Aug 2008 11:54:09 +0400 From: "Igor Kovalenko" MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_141104_26617605.1218959649810" Subject: [Qemu-devel] [PATCH] sparc64 correct 32bit carry flag for add instruction Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org ------=_Part_141104_26617605.1218959649810 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi! The attached sparc64-add-carry-icc.patch should fix a problem with setting 32bit carry flag after add instruction. This at least fixes a problem with silo vprinf printing only least significant digit of integers (now it can output address where it loads kernel instead of 0x0) Please apply. -- Kind regards, Igor V. Kovalenko ------=_Part_141104_26617605.1218959649810 Content-Type: application/octet-stream; name=sparc64-add-carry-icc.patch Content-Transfer-Encoding: base64 X-Attachment-Id: f_fjzd3oh10 Content-Disposition: attachment; filename=sparc64-add-carry-icc.patch SW5kZXg6IHRhcmdldC1zcGFyYy90cmFuc2xhdGUuYwo9PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09Ci0tLSB0YXJnZXQtc3Bh cmMvdHJhbnNsYXRlLmMJKHJldmlzaW9uIDUwMTIpCisrKyB0YXJnZXQtc3BhcmMvdHJhbnNsYXRl LmMJKHdvcmtpbmcgY29weSkKQEAgLTM0OSwxNiArMzQ5LDE5IEBACiAqLwogc3RhdGljIGlubGlu ZSB2b2lkIGdlbl9jY19DX2FkZF9pY2MoVENHdiBkc3QsIFRDR3Ygc3JjMSkKIHsKLSAgICBUQ0d2 IHJfdGVtcDsKKyAgICBUQ0d2IHJfdGVtcDEsIHJfdGVtcDI7CiAgICAgaW50IGwxOwogCiAgICAg bDEgPSBnZW5fbmV3X2xhYmVsKCk7Ci0gICAgcl90ZW1wID0gdGNnX3RlbXBfbmV3KFRDR19UWVBF X1RMKTsKLSAgICB0Y2dfZ2VuX2FuZGlfdGwocl90ZW1wLCBkc3QsIDB4ZmZmZmZmZmZVTEwpOwot ICAgIHRjZ19nZW5fYnJjb25kX3RsKFRDR19DT05EX0dFVSwgZHN0LCBzcmMxLCBsMSk7CisgICAg cl90ZW1wMSA9IHRjZ190ZW1wX25ldyhUQ0dfVFlQRV9UTCk7CisgICAgcl90ZW1wMiA9IHRjZ190 ZW1wX25ldyhUQ0dfVFlQRV9UTCk7CisgICAgdGNnX2dlbl9hbmRpX3RsKHJfdGVtcDEsIGRzdCwg MHhmZmZmZmZmZlVMTCk7CisgICAgdGNnX2dlbl9hbmRpX3RsKHJfdGVtcDIsIHNyYzEsIDB4ZmZm ZmZmZmZVTEwpOworICAgIHRjZ19nZW5fYnJjb25kX3RsKFRDR19DT05EX0dFVSwgcl90ZW1wMSwg cl90ZW1wMiwgbDEpOwogICAgIHRjZ19nZW5fb3JpX2kzMihjcHVfcHNyLCBjcHVfcHNyLCBQU1Jf Q0FSUlkpOwogICAgIGdlbl9zZXRfbGFiZWwobDEpOwotICAgIHRjZ190ZW1wX2ZyZWUocl90ZW1w KTsKKyAgICB0Y2dfdGVtcF9mcmVlKHJfdGVtcDEpOworICAgIHRjZ190ZW1wX2ZyZWUocl90ZW1w Mik7CiB9CiAKICNpZmRlZiBUQVJHRVRfU1BBUkM2NAo= ------=_Part_141104_26617605.1218959649810--