[Qemu-devel] [PATCH] sparc64 add mmu tlb demap support

["Igor Kovalenko" <igor.v.kovalenko@gmail.com>]

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Hi!

This patch adds handling of explicit i/d demapping ASI writes. Tested
by examining i/d tlb dumps. This functionality is used by e.g. silo to
release mappings acquired to load kernel and initrd before proceeding
to kernel start.

Please apply.

-- 
Kind regards,
Igor V. Kovalenko

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Index: target-sparc/op_helper.c
===================================================================
--- target-sparc/op_helper.c	(revision 5331)
+++ target-sparc/op_helper.c	(working copy)
@@ -1941,6 +1941,8 @@
         }
     case 0x55: // I-MMU data access
         {
+            // TODO: auto demap
+
             unsigned int i = (addr >> 3) & 0x3f;
 
             env->itlb_tag[i] = env->immuregs[6];
@@ -1949,6 +1951,20 @@
         }
     case 0x57: // I-MMU demap
         // XXX
+        {
+            unsigned int i;
+            for (i = 0; i < 64; i++) {
+                if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                    target_ulong mask = 0xffffffffffffe000ULL;
+                    mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
+                    if ((val & mask) == (env->itlb_tag[i] & mask)) {
+                        env->itlb_tag[i] = 0;
+                        env->itlb_tte[i] = 0;
+                    }
+                    return;
+                }
+            }
+        }
         return;
     case 0x58: // D-MMU regs
         {
@@ -2018,6 +2034,21 @@
             return;
         }
     case 0x5f: // D-MMU demap
+        {
+            unsigned int i;
+            for (i = 0; i < 64; i++) {
+                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                    target_ulong mask = 0xffffffffffffe000ULL;
+                    mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
+                    if ((val & mask) == (env->dtlb_tag[i] & mask)) {
+                        env->dtlb_tag[i] = 0;
+                        env->dtlb_tte[i] = 0;
+                    }
+                    return;
+                }
+            }
+        }
+        return;
     case 0x49: // Interrupt data receive
         // XXX
         return;