Re: [Qemu-devel] [PATCH] sparc64 support TSB related MMU registers

[Igor Kovalenko <igor.v.kovalenko@gmail.com>]

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On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
> On 4/24/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Hi!
>>
>>  This change allows reading ultrasparc I/D MMU TSB tag target register
>>  and TSB pointer register (8k and 64k).
>>  Linux kernel uses TSB for memory management, and with this change it
>>  now can use early allocation routines.
>>
>>  I'm testing with linux-2.6.29.1 minimalistic sparc64 uniprocessor
>>  build, now kernel is able to start build device tree.
>>  Without the change kernel was not able to handle D-MMU miss while
>>  creating first device tree node.
>>  Currently it stops shortly after building device tree, trying to find
>>  out path to console.
>
> Nice, though I didn't notice any visible improvement in my tests.

Here is the missing part in qemu-sparc64-mmu-pagesize.patch
This fixes TLB match code to respect page size, otherwise 4M page
mappings may be not found.
Also this corrects a typo in get_physical_address_code which uses a
register from DMMU instead of IMMU.

Please apply.

get_physical_address_data/code probably needs some code reuse refactoring.

>>  (PS with openbios instance-to-path method fails in client interface
>>  call, in the same way
>>  it fails without loading kernel when I try invoking get-instance-path
>>  on stdin handle from command prompt.
>>  there fmove invokes memmove() with size argument looking like some
>>  pointer which leads to unhandled D-MMU fault)
>
> Similar very obscure problem was fixed with PPC (r481), the bug was
> with the PCI nodes.

Here (r484) on sparc64 it hangs in the same place.

-- 
Kind regards,
Igor V. Kovalenko

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Index: qemu-trunk/target-sparc/helper.c
===================================================================
--- qemu-trunk.orig/target-sparc/helper.c
+++ qemu-trunk/target-sparc/helper.c
@@ -404,7 +404,7 @@ static int get_physical_address_data(CPU
         }
         // ctx match, vaddr match, valid?
         if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
-            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL) &&
+            (address & mask) == (env->dtlb_tag[i] & mask) &&
             (env->dtlb_tte[i] & 0x8000000000000000ULL)) {
             // access ok?
             if (((env->dtlb_tte[i] & 0x4) && is_user) ||
@@ -420,8 +420,8 @@ static int get_physical_address_data(CPU
 #endif
                 return 1;
             }
-            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
-                (address & ~mask & 0x1fffffff000ULL);
+            *physical = ((env->dtlb_tte[i] & mask) | (address & ~mask)) &
+                        0x1ffffffe000ULL;
             *prot = PAGE_READ;
             if (env->dtlb_tte[i] & 0x2)
                 *prot |= PAGE_WRITE;
@@ -467,7 +467,7 @@ static int get_physical_address_code(CPU
         }
         // ctx match, vaddr match, valid?
         if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
-            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL) &&
+            (address & mask) == (env->itlb_tag[i] & mask) &&
             (env->itlb_tte[i] & 0x8000000000000000ULL)) {
             // access ok?
             if ((env->itlb_tte[i] & 0x4) && is_user) {
@@ -481,8 +481,8 @@ static int get_physical_address_code(CPU
 #endif
                 return 1;
             }
-            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
-                (address & ~mask & 0x1fffffff000ULL);
+            *physical = ((env->itlb_tte[i] & mask) | (address & ~mask)) &
+                        0x1ffffffe000ULL;
             *prot = PAGE_EXEC;
             return 0;
         }
@@ -490,7 +490,7 @@ static int get_physical_address_code(CPU
 #ifdef DEBUG_MMU
     printf("TMISS at 0x%" PRIx64 "\n", address);
 #endif
-    env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
+    env->immuregs[6] = (address & ~0x1fffULL) | (env->immuregs[1] & 0x1fff);
     env->exception_index = TT_TMISS;
     return 1;
 }