From: Igor Kovalenko <igor.v.kovalenko@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH] sparc64 fix context value for ITLB fault
Date: Tue, 28 Apr 2009 00:10:08 +0400 [thread overview]
Message-ID: <b2fa41d60904271310p3c87ec75sed785bbe07a6f841@mail.gmail.com> (raw)
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Revert previous change to get_physical_address_code:
I/D MMU context register is shared, so using dmmuregs[1] is correct
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
[-- Attachment #2: qemu-sparc64-fix-immu-context.patch --]
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Index: qemu-trunk/target-sparc/helper.c
===================================================================
--- qemu-trunk.orig/target-sparc/helper.c
+++ qemu-trunk/target-sparc/helper.c
@@ -490,7 +490,7 @@ static int get_physical_address_code(CPU
#ifdef DEBUG_MMU
printf("TMISS at 0x%" PRIx64 "\n", address);
#endif
- env->immuregs[6] = (address & ~0x1fffULL) | (env->immuregs[1] & 0x1fff);
+ env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
env->exception_index = TT_TMISS;
return 1;
}
next reply other threads:[~2009-04-27 20:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-04-27 20:10 Igor Kovalenko [this message]
2009-04-28 16:01 ` [Qemu-devel] [PATCH] sparc64 fix context value for ITLB fault Blue Swirl
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