On Mon, Jul 20, 2009 at 10:49 AM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On Mon, Jul 20, 2009 at 12:19 AM, Igor
> Kovalenko<igor.v.kovalenko@gmail.com> wrote:
>> tl and tsptr of members sparc64 cpu state must be changed
>> simultaneously to keep trap state window in sync with current
>> trap level. Currently translation of store to tl does not change
>> tsptr, which leads to corrupt trap state on corresponding
>> trap level.
>>
>> This patch removes tsptr from sparc64 cpu state and replaces
>> all uses with call to helper routine.
>
> I'd rather have the stores to TL fixed instead of introducing a
> helper. A new function to set both TL and tsptr may help. Which stores
> to TL do not change tsptr?
The problem is with translate.c portion about handling wrpr
(it sets tl only). My idea is that even remote possibility of tsptr
and tl going out of sync guarantees killing one of them. Since
tl is a real register I decided to loose tsptr.

>
> On CPU reset, TL should be MAXTL for POR and MIN(TL+1, MAXTL) in other
> cases but your patch would set it to 0.

Right but please see that original code did not done that either :)

Please see updated patch which additionally sets tl=maxtl.
I decided to populate trap level, trap type and pstate with
power-on reset values since other reset types are not handled yet.

-- 
Kind regards,
Igor V. Kovalenko