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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb72facf9sm28472904f8f.13.2025.10.01.09.25.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Oct 2025 09:25:25 -0700 (PDT) Message-ID: Date: Wed, 1 Oct 2025 18:25:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 05/27] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, shameerkolothum@gmail.com References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-6-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20250929133643.38961-6-skolothumtho@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 9/29/25 3:36 PM, Shameer Kolothum wrote: > Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need > different callback handling in upcoming patches. This also adds a > CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled > at compile time. Because we now include CONFIG_DEVICES in the header to > check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to > be changed as well. > > The “accel” property isn’t user visible yet, it will be introduced in > a later patch once all the supporting pieces are ready. > > Reviewed-by: Nicolin Chen > Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Eric > --- > hw/arm/Kconfig | 5 ++++ > hw/arm/meson.build | 3 ++- > hw/arm/smmuv3-accel.c | 52 +++++++++++++++++++++++++++++++++++++++++ > hw/arm/smmuv3-accel.h | 27 +++++++++++++++++++++ > hw/arm/smmuv3.c | 5 ++++ > include/hw/arm/smmuv3.h | 3 +++ > 6 files changed, 94 insertions(+), 1 deletion(-) > create mode 100644 hw/arm/smmuv3-accel.c > create mode 100644 hw/arm/smmuv3-accel.h > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 3baa6c6c74..157c0f3517 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -12,6 +12,7 @@ config ARM_VIRT > select ARM_GIC > select ACPI > select ARM_SMMUV3 > + select ARM_SMMUV3_ACCEL > select GPIO_KEY > select DEVICE_TREE > select FW_CFG_DMA > @@ -625,6 +626,10 @@ config FSL_IMX8MP_EVK > config ARM_SMMUV3 > bool > > +config ARM_SMMUV3_ACCEL > + bool > + depends on ARM_SMMUV3 && IOMMUFD > + > config FSL_IMX6UL > bool > default y > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index dc68391305..bcb27c0bf6 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c')) > -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) > +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) > +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) > arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) > arm_ss.add(when: 'CONFIG_XEN', if_true: files( > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > new file mode 100644 > index 0000000000..79f1713be6 > --- /dev/null > +++ b/hw/arm/smmuv3-accel.c > @@ -0,0 +1,52 @@ > +/* > + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd > + * Copyright (C) 2025 NVIDIA > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/arm/smmuv3.h" > +#include "smmuv3-accel.h" > + > +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *sbus, > + PCIBus *bus, int devfn) > +{ > + SMMUDevice *sdev = sbus->pbdev[devfn]; > + SMMUv3AccelDevice *accel_dev; > + > + if (sdev) { > + return container_of(sdev, SMMUv3AccelDevice, sdev); > + } > + > + accel_dev = g_new0(SMMUv3AccelDevice, 1); > + sdev = &accel_dev->sdev; > + > + sbus->pbdev[devfn] = sdev; > + smmu_init_sdev(bs, sdev, bus, devfn); > + return accel_dev; > +} > + > +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, > + int devfn) > +{ > + SMMUState *bs = opaque; > + SMMUPciBus *sbus = smmu_get_sbus(bs, bus); > + SMMUv3AccelDevice *accel_dev = smmuv3_accel_get_dev(bs, sbus, bus, devfn); > + SMMUDevice *sdev = &accel_dev->sdev; > + > + return &sdev->as; > +} > + > +static const PCIIOMMUOps smmuv3_accel_ops = { > + .get_address_space = smmuv3_accel_find_add_as, > +}; > + > +void smmuv3_accel_init(SMMUv3State *s) > +{ > + SMMUState *bs = ARM_SMMU(s); > + > + bs->iommu_ops = &smmuv3_accel_ops; > +} > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > new file mode 100644 > index 0000000000..70da16960f > --- /dev/null > +++ b/hw/arm/smmuv3-accel.h > @@ -0,0 +1,27 @@ > +/* > + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd > + * Copyright (C) 2025 NVIDIA > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_ARM_SMMUV3_ACCEL_H > +#define HW_ARM_SMMUV3_ACCEL_H > + > +#include "hw/arm/smmu-common.h" > +#include CONFIG_DEVICES > + > +typedef struct SMMUv3AccelDevice { > + SMMUDevice sdev; > +} SMMUv3AccelDevice; > + > +#ifdef CONFIG_ARM_SMMUV3_ACCEL > +void smmuv3_accel_init(SMMUv3State *s); > +#else > +static inline void smmuv3_accel_init(SMMUv3State *s) > +{ > +} > +#endif > + > +#endif /* HW_ARM_SMMUV3_ACCEL_H */ > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index bcf8af8dc7..ef991cb7d8 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -32,6 +32,7 @@ > #include "qapi/error.h" > > #include "hw/arm/smmuv3.h" > +#include "smmuv3-accel.h" > #include "smmuv3-internal.h" > #include "smmu-internal.h" > > @@ -1882,6 +1883,10 @@ static void smmu_realize(DeviceState *d, Error **errp) > SysBusDevice *dev = SYS_BUS_DEVICE(d); > Error *local_err = NULL; > > + if (s->accel) { > + smmuv3_accel_init(s); > + } > + > c->parent_realize(d, &local_err); > if (local_err) { > error_propagate(errp, local_err); > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index d183a62766..bb7076286b 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -63,6 +63,9 @@ struct SMMUv3State { > qemu_irq irq[4]; > QemuMutex mutex; > char *stage; > + > + /* SMMU has HW accelerator support for nested S1 + s2 */ > + bool accel; > }; > > typedef enum {