From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH-4.2 v1 2/6] target/riscv: Remove strict perm checking for CSR R/W
Date: Thu, 25 Jul 2019 11:52:04 -0700 [thread overview]
Message-ID: <b415f5b51e09418760b95e5c73fad5e68b97f173.1564080680.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564080680.git.alistair.francis@wdc.com>
The privledge check based on the CSR address mask 0x300 doesn't work
when using Hypervisor extensions so remove the check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0d4586760..af3b762c8b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -797,9 +797,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
int read_only = get_field(csrno, 0xC00) == 3;
- if ((write_mask && read_only) || (env->priv < csr_priv)) {
+ if (write_mask && read_only) {
return -1;
}
#endif
--
2.22.0
next prev parent reply other threads:[~2019-07-25 18:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-25 18:51 [Qemu-devel] [PATCH-4.2 v1 0/6] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 1/6] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-29 14:33 ` Philippe Mathieu-Daudé
2019-07-25 18:52 ` Alistair Francis [this message]
2019-07-25 21:47 ` [Qemu-devel] [Qemu-riscv] [PATCH-4.2 v1 2/6] target/riscv: Remove strict perm checking for CSR R/W Jonathan Behrens
2019-07-26 20:24 ` Alistair Francis
2019-07-26 21:00 ` Jonathan Behrens
2019-07-26 22:28 ` Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-26 15:22 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-07-29 14:28 ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-07-29 17:32 ` Chih-Min Chao
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-07-29 14:31 ` Philippe Mathieu-Daudé
2019-07-29 16:56 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-07-30 18:32 ` Alistair Francis
2019-07-30 8:49 ` [Qemu-devel] " Christophe de Dinechin
2019-07-30 18:33 ` Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 5/6] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-07-26 17:40 ` Chih-Min Chao
2019-07-26 20:20 ` Alistair Francis
2019-07-25 18:52 ` [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names Alistair Francis
2019-07-29 15:19 ` Chih-Min Chao
2019-07-30 18:37 ` Alistair Francis
2019-07-31 8:10 ` Chih-Min Chao
2019-08-05 17:49 ` Alistair Francis
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