From: <Conor.Dooley@microchip.com>
To: <atishp@rivosinc.com>
Cc: <qemu-devel@nongnu.org>, <alistair.francis@wdc.com>,
<bin.meng@windriver.com>, <palmer@dabbelt.com>,
<qemu-riscv@nongnu.org>
Subject: Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree
Date: Mon, 28 Nov 2022 21:10:03 +0000 [thread overview]
Message-ID: <b42e75c6-8c52-025e-35ef-326537ccc90b@microchip.com> (raw)
In-Reply-To: <CAHBxVyGVigqBLLS9vqas+uq=Joyr2F6ir0zqtg+0y2GaTCyX-A@mail.gmail.com>
On 28/11/2022 20:41, Atish Kumar Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Nov 28, 2022 at 12:38 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 28/11/2022 20:16, Atish Kumar Patra wrote:
>>> On Thu, Nov 24, 2022 at 5:17 AM Conor Dooley <conor.dooley@microchip.com> wrote:
>>>>
>>>> On Wed, Aug 24, 2022 at 03:17:00PM -0700, Atish Patra wrote:
>>>>> Qemu virt machine can support few cache events and cycle/instret counters.
>>>>> It also supports counter overflow for these events.
>>>>>
>>>>> Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
>>>>> capabilities. There are some dummy nodes added for testing as well.
>>>>
>>>> Hey Atish!
>>>>
>>>> I was fiddling with dumping the virt machine dtb again today to check
>>>> some dt-binding changes I was making for the isa string would play
>>>> nicely with the virt machine & I noticed that this patch has introduced
>>>> a new validation failure:
>>>>
>>>> ./build/qemu-system-riscv64 -nographic -machine virt,dumpdtb=qemu.dtb
>>>>
>>>> dt-validate -p ../linux/Documentation/devicetree/bindings/processed-schema.json qemu.dtb
>>>> /home/conor/stuff/qemu/qemu.dtb: soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281, 2, 2, 524284, 65561, 65561, 524280, 65563, 65563, 524280, 65569, 65569, 524280, 0, 0, 0, 0, 0]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
>>>> From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/simple-bus.yaml
>>>>
>>>> I assume this is the aforementioned "dummy" node & you have no intention
>>>> of creating a binding for this?
>>>>
>>>
>>> It is a dummy node from Linux kernel perspective. OpenSbi use this
>>> node to figure out the hpmcounter mappings.
>>
>> Aye, but should it not have a binding anyway, since they're not
>> meant to be linux specific?
>>
> It is documented in OpenSBI.
> https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
>
> Are you suggesting that any non-Linux specific DT nodes should be part
> of Linux DT binding as well ?
I thought the point was that they were *not* meant to be linux specific,
just happening to be housed there.
next prev parent reply other threads:[~2022-11-28 21:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 22:16 [PATCH v14 0/5] Improve PMU support Atish Patra
2022-08-24 22:16 ` [PATCH v14 1/5] target/riscv: Add sscofpmf extension support Atish Patra
2022-08-24 22:16 ` [PATCH v14 2/5] target/riscv: Simplify counter predicate function Atish Patra
2022-08-24 22:16 ` [PATCH v14 3/5] target/riscv: Add few cache related PMU events Atish Patra
2022-08-24 22:17 ` [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-11-24 13:16 ` Conor Dooley
2022-11-28 20:16 ` Atish Kumar Patra
2022-11-28 20:38 ` Conor.Dooley
2022-11-28 20:41 ` Atish Kumar Patra
2022-11-28 21:10 ` Conor.Dooley [this message]
2022-11-29 7:08 ` Andrew Jones
2022-11-29 7:32 ` Conor.Dooley
2022-11-29 9:27 ` Atish Kumar Patra
2022-11-29 9:42 ` Conor.Dooley
2022-11-29 23:54 ` Conor.Dooley
2022-11-30 8:13 ` Atish Kumar Patra
2022-11-30 8:31 ` Conor.Dooley
2022-08-24 22:17 ` [PATCH v14 5/5] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-09-19 22:08 ` [PATCH v14 0/5] Improve PMU support Alistair Francis
2022-09-20 8:36 ` Atish Kumar Patra
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